Symposium Organizers
Caroline Bonafos CEMES/CNRS
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Panagiotis Dimitrakis NCSR "Demokritos"
G1: Nano-Crystal Memory I
Session Chairs
Thierry Baron
Caroline Bonafos
Yann Leroy
Abdelillah Slaoui
Monday PM, April 05, 2010
Room 2011 (Moscone West)
9:30 AM - **G1.1
Nanocrystal Memories.
Thierry Baron 1 , Barbara De Salvo 2 , Gabriel Molas 2 , Pierre Mur 2 , Abdelkader Souifi 3 , Bassem Salem 1 , Karim Aissou 4 , Redouane Borsali 4 , Guillaume Gay 2
1 LTM, CNRS, Grenoble France, 2 Leti, CEA, Grenoble France, 3 INL, CNRS, Lyon France, 4 CERMAV, CNRS, Grenoble France
Show AbstractDiscrete storage nodes memories have serious potential for pushing further the scaling limits of conventional NAND Flash. Si nanocrystals memories have reached the maturity to be integrated in conventional CMOS production lines. For future memory generation, a key point will be to increase the density of charge on the granular floating gate to keep a significant threshold voltage shift and the advantage of the discrete storage node. For this, we have investigated different strategy among them (i) increasing the Si NC density, (ii) coupling Si NC with another traps materials, (iii) using metallic particle instead of semiconducting one. In the case of metallic nanoparticles or III-V semiconductor nanocrystals granular floating gate an improvement of the retention time as compared to Si nanocrystals floating gate technology should be observed, due to their barrier height with respect to Si and SiO2. Moreover their process technology could be fully CMOS compatible. Another improvement could be reached in using organized nanoparticles which guarantee the accurate control, in a reproducible way, of the electrical properties of the devices (programming windows). The challenge is to develop a CMOS compatible technology to produce an ordered array of nanoparticles with a high density. The conventional lithographic tools cannot fulfil this requirement. We have developed a technology on industrial 8 inches wafer based on copolymer diblocks self-assembling properties to produced hexagonally ordered nanoparticles. The bottleneck for this technology is the relatively low nanoparticles density (midlle of 1011 cm-2) which is obtained. We propose an original method to reach a value close to 1012 cm-2. Moreover, we will present a bottom-up technology to fabricate nanocrytals floating gate memory with Si nanowires used as a FET channel.
10:00 AM - G1.2
Annealing Effects on Si Nanocrystal Nonvolatile Memories.
Panagiotis Dimitrakis 1 , C. Bonafos 2 , S. Schamm 2 , G. Ben Assayag 2 , P. Normand 1
1 Inst. of Microelectronics, NCSR Demokritos, Aghia Paraskevi Greece, 2 CEMES, CNRS, Universite de Toulouse, Toulouse Greece
Show AbstractLow energy ion beam synthesis has been used extensively for the formation of nanoparticles in dielectric matrices. During the last decade, a significant number of papers have been published demonstrating the synthesis mainly of Si nanocrystals (NCs) in SiO2 layers for nonvolatile memory applications. A breakthrough in ion beam synthesis was the fabrication NC-NVMs utilizing Si beams with implantation energies in the regime <2keV [1,2] allowing for the synthesis of NCs into very thin dielectrics (<10nm)). For the optimization of memory performance and NC functionality a comprehensive study on the effect of post implantation annealing (PIA) conditions were carried out. In the present paper, we report on the results of PIA conditions on the functionality and the final memory performance of NC-NVM MOS capacitors fabricated on p-Si substrates. The Si-NCs were formed by implantation of 1keV Si atoms into 7nm high-quality SiO2 layers; where necessary additional TEOS SiO2 layers were deposited. Two different PIA approaches have been studied. According to first, the NC NVM memory devices are realized following one-step PIA process. There the annealing temperature was in the range of 800-1050C and the annealing ambient was O2 diluted in N2 with concentrations ranging from 0 to 5%. In the second approach, a two-step annealing process is followed. During the first step the coalescence of Si-atoms and the formation of NCs occur while the second step is used in order to enhance the functionality of NC for charge-storage. Improved electrical and TEM characterization techniques were used to study and explain the role of temperature and annealing environment on the charge-storage properties of the fabricated devices.[1] P.Normand et al, Appl.Phys.Lett. 83, 168 (2003)[2] P.Dimitrakis et al. Solid-State Electron. 48, 1511 (2004)
10:15 AM - G1.3
MOS Memory With High Density PtSi Nanocrystals.
Bei Li 1 , Jianlin Liu 1
1 Quantum Structures Laboratory, Electrical Engineering, University of California, Riverside, Riverside, California, United States
Show AbstractNonvolatile memories with semiconductor or metal nanocrystals as storage elements in metal-oxide-semiconductor field effect transistors have been intensively investigated by researchers in both industry and academic institutions. Compared with semiconductor, metal nanocrystal devices perform better in terms of large memory window and fast program/erase speed. However the drawback of the poor thermal stability makes the application of metal nanocrystal memory difficult. To address this problem, silicide nanocrystals are believed as a candidate to replace metal nanocrystals because of their metallic properties and better thermal stability. TiSi2 [1], CoSi2 [2-3], and NiSi [4] nanocrystals have been reported with good memory performance. However almost all the processes involve either high temperature annealing or pre-mixed silicide targets preparation. In this presentation, we report a new method to synthesize PtSi nanocrystals with high density of 1.5 × 1012 cm-2 and size of ~5nm. The nanocrystal formation takes advantage of Vapor-Solid-Solid (VSS) process, where metal nano-particles, as catalysts, were pre-formed on SiO2/Si substrate, followed by silicide formation through introducing SiH4 into the metal catalysts in a chemical vapor deposition system. The metal that we chose for VSS silicide nanocrystal growth is platinum because the Fermi level of PtSi is within Si band gap, which benefits the retention time by localizing the charge into the deep quantum well formed at PtSi side. Using the nanocrystals with density of 1.5 × 1012 cm-2, we fabricated a metal-oxide-semiconductor memory device and tested the charging/discharging characteristics by Fowler-Nordheim mechanism. From the experiment results, an evident and large memory window was observed and defect-relative charging effect has been ruled out by comparing with a control device with no nanocrystal embedded between oxide layers. Program, erasing and retention performances were tested and good device performances were obtained. The work suggests that silicide nanocrystal memories show greater promise toward nanocrystal memory applications.References[1] Y. Zhu, B. Li, J. L. Liu, G. F. Liu, and J. A. Yarmoff, “TiSi2/Si heteronanocrystal metal-oxide-semiconductor-field-effect-transistor memory,” Appl. Phys. Lett., Vol. 89, No. 23, p. 233113, 2006.[2] B. Li, and J. L. Liu, “CoSi2-coated Si nanocrystal memory,” J. Appl. Phys., Vol. 105, No. 8, p. 084905, Apr. 2009.[3] J. H. Kim, J. Y. Yang, J. S. Lee, and J. P. Hong, “Memory characteristics of cobalt-silicide nanocrystals embedded in HfO2 gate oxide for nonvolatile nanocrystal falsh devices,” Appl. Phys. Lett., Vol. 92, p. 013512, Jan. 2008.[4] W. R. Chen, T. C. Chang, J. L. Yeh, S. M. Sze, and C. Y. Chnag, “Reliability characteristics of NiSi nanocrystals embedded in oxide and nitride layers for nonvolatile memory application,” Appl. Phys. Lett., Vol. 92, No. 15, p. 152114, Apr. 2008.
10:30 AM - G1.4
Theoretical Characterization of a Nanocrystal Layer for Nonvolatile Memory Applications.
Yann Leroy 1 , Dumitru Armeanu 1 , Anne-Sophie Cordan 1
1 , InESS / CNRS-UdS, Illkirch France
Show AbstractOn the road to miniaturization, nanocrystal layers are promising as floating gate in nonvolatile flash memories. Although much experimental work has been devoted to the study of these new memory devices, only few theoretical models exist to help the experimentalists to understand the physical phenomena encountered and explain the behavior of the device.We have developed a model based on the geometrical and physical properties of the elementary structure of a nanocrystal flash memory, i.e. one nanocrystal embedded in an oxide between the channel and the gate electrodes. To obtain a fine analysis of the observed phenomena, several specific hypotheses have been taken into account. Concerning the channel, the contribution of the subbands is explicitly included. In the case of an electrode with a quasi-continuum of energy levels, we replace the continuum by equivalent sets of 2D subbands in order to be able to isolate the energy range that really contributes to the charging/discharging of the nanocrystal. The properties of the materials (bulk band structure, dielectric permittivity, ...) can be easily set as well as the geometrical specifications of the elementary structure (nanocrystal radius, tunnel and control oxyde thicknesses, ...).The behavior of a layer of nanocrystals is described according to a statistical approach starting from single nanocrystal results. This method allows us to take into account the fluctuations of geometrical parameters. Thus we are able to simulate various types of materials for the nanocrystals (Si, Ge, ...), the oxide layer (SiO2, HfO2, ...) and the electrodes, for both a single nanocrystal and layers of nanocrystals.Finally, a nanocrystal layer can be characterized through its electrical responses, helping then to the optimization of the parameters (geometrical, materials) for new efficient nonvolatile memories.
10:45 AM - G1.5
InGaAs Floating Quantum Dot Gate Non-volatile Memory Devices.
Pik-Yiu Chan 1 , Mukesh Gogna 1 , Ernesto Suarez 1 , Fuad Alamoody 1 , Supriya Karmakar 1 , Barry Miller 1 , John Ayers 1 , Faquir Jain 1
1 Electrical and Computer Engineering, University of Connecticut, Storrs, Connecticut, United States
Show AbstractRecently, there have been many reports of implementing InGaAs field-effect transistors (FETs) either on InP or directly on Si substrates. Due to its high electron mobility, indium gallium arsenide high electron mobility transistors (HEMTs) are one of the fastest transistors on the market. Unlike HEMTs, InGaAs FETs in MOS or CMOS configuration require use of a gate insulator that provides minimum interface states resulting in reproducible threshold voltage behavior. The UConn group has successfully fabricated InGaAs FETs with lattice-matched II-VI layers serving as the gate insulator grown by MOCVD [Jain et al, JEM, 38, pp- 1574-1578, August 2009]. This paper presents data and simulation results on InGaAs based quantum dot floating gate non-volatile memory structures. The memory structure incorporates GeOx-cladded germanium quantum dots, site-specific self-assembled over the II-VI gate insulator over the p-InGaAs region (between the n-type source and drain). The details of site-specific self-assembly of GeOx-Ge quantum dots to realize nonvolatile memories on Si substrate was recently reported by Gogna et al. [2009 Nanodevices for Defense and Security Conference, September 30-October 2, Fort Lauderdale, Fl] by the UConn group.In this presentation, we also discuss the material aspects of fabrication of nonvolatile memory devices, combining processing of InGaAs FET and incorporation of GeOx-Ge quantum dots as the floating gate. The process is compatible with standard CMOS processing steps. The growth of ZnMgSe-ZnS gate layers is carried out in a photoassisted metalorganic chemical vapor deposition (MOCVD) reactor under temperatures of 500oC. Two layers of GeOx-Ge dots are self-assembled on II-VI gate insulators at room temperature. However, the anneal cycle following dot deposition involves heating to about 450oC.In summary, preliminary experimental results and theoretical modeling of InGaAs (on InP) nonvolatile memory devices are reported in this paper.
11:30 AM - G1.6
Electrical Characterization of Low Energy Ge+ Implanted Si3N4 Films With HfO2/SiO2 Stack Tunnel Dielectric for Non-volatile Memory Application.
Bhabani Sahu 1 , Marzia Carrada 1 , Abdelillah Slaoui 1 , Pierre-Eugene Coulon 2 , Jesse Groenen 2 , Caroline Bonafos 2 , Sandrine Lhostis 3
1 InESS, InESS-UDS-CNRS, Strasbourg France, 2 Groupe Nanomat , CEMES-CNRS – Université de Toulouse, Toulouse France, 3 , ST Microelectronics, Crolles France
Show AbstractThe use of high-k dielectrics on Si as a tunnel layer offers a lower electron barrier height at the dielectric/Si interface and larger physical thickness, resulting in faster programming and longer retention than conventional SiO2 tunnel dielectric. Unfortunately, the high-k/Si interface is marred by the formation of silicates and/or silicides. In this regard, the use of a stack dielectric, such as HfO2/SiO2 can be of interest. In this work, Ge nanocrystals (Ge-ncs) embedded in Si3N4 dielectrics with HfO2/SiO2 tunnel dielectrics having an equivalent oxide thickness (EOT) of 2.6 nm have been synthesized with low energy ion implantation (3 to 5 keV) and subsequent annealing at 800 °C for 30 min in N2 ambient. The top Si3N4 with a thickness of ~10 nm and bottom HfO2 with a thickness of ~ 4.7 nm have been deposited with electron cyclotron resonance-chemical vapor deposition (ECR-CVD) and metal organic chemical vapor deposition (MOCVD), respectively. The Raman spectra and high resolution transmission electron microscopy (HRTEM) images clearly indicate the evidence of self assembled Ge-ncs within the top Si3N4 gate dielectric. C-V and G-V measurements exhibit significant effects of implant energy and dose on the electrical performance of the MOS capacitor. A large memory window of 2.9 V has been achieved at relatively low sweeping voltage of ± 6 V for the samples implanted with a dose of 1 × 1016 cm-2 at 5 keV and annealed at an optimum temperature of 800 oC. The memory window further increases to 4.53 V with increasing the dose to 1.5 × 1016 cm-2. Frequency dependent C-V and G-V curves indicate negligible contribution from interfacial defects towards the charge storage capability. All the samples exhibit sharp and single conductance peaks with almost constant full width at half maxima (FWHM) during program and erase process, thereby indicating single electron charging in Ge nanocrystals. These results indicate a strong memory effect at relatively low programming voltages (≤ 6 V) due to the presence of Ge-ncs very close to the Si3N4/HfO2 interface. The EOT of the tunnel oxide separating the Ge-ncs from the channel (Si substrate) is of about 3.4 nm only. So, the combination of suitable energy and dose of Ge implants, annealing temperature, and choice of Si3N4/HfO2/SiO2 stack dielectric can be suitable for the fabrication of low operating voltage non-volatile memory devices.
11:45 AM - G1.7
Ultra-low Energy Ion Implantation of Si into SiO2 or SiN on Top of HfO2-based Layers for Non-volatile Memory Applications.
Pierre-Eugene Coulon 1 , Caroline Bonafos 1 , Gerard Benassayag 1 , Sylvie Schamm-Chardon 1 , Sandra Boussetta 1 , Beatrice Pecassou 1 , Abdelillah Slaoui 2 , Sahu Babhani 2 , Marzia Carrada 2 , Sandrine Lhostis 3
1 , CEMES, Toulouse France, 2 , InESS, Strasbourg France, 3 , ST Microelectronics, Crolles France
Show AbstractThe use of nanocrystals (NCs) embedded in a SiO2 matrix as charge storage elements in novel non-volatile memory (NVM) devices has been widely explored in the last decade. The replacement of the polysilicon layer of a flash memory by a 2D NC array presents several advantages but the fundamental trade-off between programming and data retention has not yet been overcome. In principle low voltage NVM can be achieved by using high-k dielectrics as gate oxide. Several approaches have been explored to fabricate ordered arrays of Si-NCs in SiO2 but the transfer to high–k materials is not obvious due in particular to fast O2 diffusion in these high-k layers1. The fabrication of the NCs is carried out using an innovative method, ultra low energy (≤5 keV) ion implantation (ULE-II) into thin layers in order to form after rapid thermal annealing a controlled 2D array of Si NCs. This technique has been successfully used in the past for the controlled fabrication of a 2D-array (plane) of Si-NCs within very thin (<10 nm) SiO2 matrix2. We have shown in a preliminary work that the implantation of Si directly into HfO2 leads to the formation of SiO2–rich regions at the projected range due to the oxidation of the implanted Si atoms 3. This anomalous oxidation that takes place at room temperature is due to humidity penetration in damaged layers and is also present, to a lower extent, when Si is implanted into SiO2 4.We present an innovative architecture where HfO2 acts as tunnel oxide between the Si substrate and the Si NCs embedded in a SiO2 or SiN top layer. Structural and chemical studies are carried out at the atomic scale by High Resolution Electron Microscopy (HREM) and Electron Energy Loss Spectroscopy in scanning mode by using a nanometer probe (STEM-EELS). They are correlated to the electrical properties and memory performance through testing of MIS capacitors and transistors.1 M. Fanciulli, M. Perego, C. Bonafos, A. Mouti, S. Schamm, G.Benassayag, Advances in Science and Technology 51, 156-166 (2006)2 C. Bonafos, M. Carrada, N. Cherkashin, H. Coffin, D. Chassaing, G. Ben Assayag and A. Claverie, T. Müller and K. H. Heinig, M. Perego and M. Fanciulli, P. Dimitrakis and P. Normand J. Appl. Phys. 95, 5696 (2004)3 P. E. Coulon, K. Chan Shin Yu, S. Schamm, G. Ben Assayag, B. Pecassou, A. Slaoui, S.Bhabani, M. Carrada, S. Lhostis and C. Bonafos, Mater. Res. Soc. Symp. Proc. 1160-H01-03(2009)4 A. Claverie, C. Bonafos, G. Ben Assayag, S. Schamm, N. Cherkashin,V. Paillard, , P. Dimitrakis, E. Kapetenakis, D. Tsoukalas, T. Muller, B. Schmidt, K. H. Heinig, M. Perego, M. Fanciulli, D. Mathiot, M. Carrada and P. Normand, Diffusion in Solids and Liquids, 258-260, 531 (2006)
12:00 PM - G1.8
Charge Trapping Sites in nc-RuO Embedded ZrHfO High-k Nonvolatile Memories.
Chen-Han Lin 1 , Yue Kuo 1
1 Thin Film Nano & Microelectronics Research Lab, Texas A&M University, College Station , Texas, United States
Show AbstractNonvolatile memories based on embedding the discrete nanocrystalline ruthenium oxide (nc-RuO) in the high-k film have been successfully fabricated [1,2]. This kind of device has charge storage capability and a long retention time. Our previous study showed that both electrons and holes could be trapped to the film depending on the polarity and magnitude of the gate bias [1]. Since there are several possible charge trapping sites in the dielectric layer, e.g., the bulk high-k film, high-k/Si interface, bulk nc-RuO, or nc-RuO/high-k interface, it is imperative to identify the responsible sites. In addition, it is also necessary to know whether electrons and holes are trapped at same or different sites. In this paper, authors investigated the electron- and hole-trapping characteristics in MOS capacitors that embed nc-RuO in the Zr-doped HfO2 (ZrHfO) high-k film. The p-Si (100) wafer was used as the substrate. The ZrHfO (tunnel oxide)/nc-RuO/ZrHfO (control oxide) stack was deposited by sputtering in one pump down without breaking the vacuum, which was subsequently annealed by RTA at 950°C for 1min under the N2/O2 ambient. The Al film was sputter deposited, defined into the gate electrode (7.85×10-5cm2), and annealed at 300°C for 5 min under the H2/N2 atmosphere. Al film was also deposited for the wafer backside ohmic contact. The constant voltage stress (CVS) study showed that the control sample, i.e., ZrHfO without embedded nc-RuO, did not have charge storage capability under the experiment condition of ±9V for 10s. Therefore, bulk ZrHfO and ZrHfO/Si interface can be ruled out as the charge trapping sites in the embedded sample. However, when the capacitor was stressed at Vg = -9V and +9V separately, the flatband voltage (VFB) shifted by -1V and 0.58V, correspondingly. The former is due to hole trapping and the latter is from electron trapping. Therefore, bulk nc-RuO or the nc-RuO/ZrHfO interface is responsible for the charge trapping. The frequency-dependent capacitance-voltage (C-V) characterization method showed that only the trapped holes, not trapped electrons, responded to the low measure frequency. Since the nc-RuO/ZrHfO interface near the Si wafer rather than the bulk nc-RuO is sensitive to the measure frequency, it is possible that the holes are trapped at the nc-RuO/ZrHfO interface site and electrons are trapped at the bulk nc-RuO site.
12:15 PM - G1.9
Co/HfO2(Al2O3) Core Shell Nanocrystal Memory.
Huimei Zhou 1 , Jian Huang 1 , Jianlin Liu 1 , James Dorman 2 , Yuanbing Mao 2 , Ya-Chuan Perng 2 , Stephanie Gachot 2 , Jane Chang 2
1 Dept of Electrical Engineering, UC Riverside, Riverside, California, United States, 2 Department of Chemical Engineering, University of California. Los Angeles, Los Angeles, California, United States
Show AbstractNonvolatile memory devices with floating nanocrystals as storage elements in metal-oxide-semiconductor field effect transistors (MOSFET) have attracted much attention from researchers in both industry and academic institutions.1–2 Different nanocrystals such as semiconductor nanocrystals, metal nanocrystals, heter-nanocrystals, double layer nanocrystals were used to improve the device performance.3-4 Here we report novel process of core shell dot by diblock co-polymer fabrication and enhanced performance of the core shell dot embedded floating gate memories. The dielectric shell, which behaves as an additional barrier, improves the retention performance.The novel core shell nano particle embedded floating gate memory fabrication process begins with a thermal oxide of about 5 nm, which was grown on Si (100) at 850 °C. HfO2 of about 3nm was grown by Atomic Layer Deposition (ALD). Co nanoparticles were aligned on the HfO2 surface by diblock copolymer process. 3nm HfO2 was grown again on the surface of the Co nanoparticles to cover and surround the Co nanoparticles. The sample was then capped with control oxide of about 15 nm in a low-temperature oxide CVD furnace. Normal capacitor fabrication process was performed afterwards to form MOS capacitors. Al2O3 was also used as shell with thickness of about 4nm to form the Co core Al2O3 shell nanocrystal memory capacitor. The memories were then characterized by Agilent 4284A LCR meter and pulse generator at room temperature. Memory effect was clearly demonstrated for the core shell dot memory and the memory window increases with the increase of sweep voltage. Writing, erasing and retention performance were characterized showing high performance. Theoretical analysis was carried out to explain the effect of the shell on the performance improvement. The result indicates that the core shell dot memories show higher promise in memory device applications. Further experiments are in progress to improve the controllability and density of the nanoparticles for the performance improvement.REFERENCE:1 Q. Wan, C. L. Lin, W. L. Liu, and T. H. Wang, Appl. Phys. Lett. 82, 4708 2003.2S. Choi, S. S. Kim, M. Chang, H. S. Hwang, S. H. Jeon, and C. W. Kim, Appl. Phys. Lett. 86, 123110 20053Chungho Lee, Tuo-Hung Hou, and Edwin Chih-Chuan Kan, IEEE Transactions on Electron Devices, Vol. 52, No. 12, 2697, DECEMBER 20054 Huimei Zhou, Reuben Gann, Bei Li, Jianlin Liu and J. A. Yarmoff, Mater. Res. Soc. Symp. Proc. Vol. 1160 (2009)
12:30 PM - **G1.10
Overview of Advanced 3D Charge-trapping Flash Memory Devices.
Hang-Ting Lue 1 , Kuang-Yeu Hsieh 1 , Rich Liu 1 , Chih-Yuan Lu 1
1 NanoTechnology R&D Department, Macronix International Co., Ltd., Hsinchu Taiwan
Show AbstractAlthough conventional floating gate (FG) Flash memory will soon go into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges are FG interference, few-electron storage and statistical limitation, poor short-channel effect, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore’s law to continue beyond another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.
G2: Advanced Flash I
Session Chairs
Albert Chin
Panagiotis Dimitrakis
Monday PM, April 05, 2010
Room 2011 (Moscone West)
2:45 PM - **G2.1
Local Charge Trapping Non-volatile Memories: First Ten Years.
Yakov Roizin 1
1 R&D, Tower Semiconductor Ltd., Migdal HaEmek Israel
Show AbstractSilicon Nitride charge trapping devices that reduce memory size by facilitating the storage of multiple bits per NVM cell have been introduced into mass production 10 years ago. They store information as charge packages at the opposite channel edges of a SONOS transistor. Electrons are stored by traps in the Si3N4 film sandwiched between non-tunnel silicon dioxide layers. Programming is performed by channel hot electrons and erase by band-to-band tunneling generated holes. The memory cell is read-out in the direction opposite to programming (NROM principle). Two bit per cell and four bit per cell (several charge levels at each channel side) devices have been developed. NROM memories are currently fabricated both in stand-alone and embedded versions by different vendors and under different brand names. In this talk we review advantages and limitations of NROM memories and technologies exploiting similar single cell structures. We focus on the material science of the memory media, device and process limitations, describe the problems related to integration and scaling down. We describe the chemical structure of the device quality silicon nitride suitable for local charge storage, its chemical content, bonding and correlation of atomic structure with material and device characteristics. The models of traps in silicon nitride developed using the results of structural measurements in combination with first-principle density fluctuation theory simulations are presented. Degradation phenomena specific for local charge trapping media are accentuated, in particular the hot hole related effects at the Si-SiO2 interface and the phenomena of lateral charge migration in the memory stack. Local charge trapping memories are compared with other NVM solutions that employ charge trapping in dielectrics. The advanced device geometries suitable for deep scaling down are considered. Advantages of local charge trapping memories in special applications requiring high temperature retention, enhanced security and radiation tolerance are demonstrated.
3:15 PM - G2.2
Stack Engineering of HfO2–based Charge Trapping Non-volatile Memory.
Ugo Russo 1 , Sabina Spiga 1 , Gabriele Congedo 1 , Alessio Lamperti 1 , Olivier Salicio 1 , Marco Fanciulli 1
1 Laboratorio MDM, CNR-INFM, Agrate Brianza Italy
Show AbstractCharge trapping (CT) memory is the most widely accepted evolution of the floating gate Flash memory concept toward the integration beyond the 32nm technology node [1]. In CT memories, the poly-Si floating gate is replaced by a trap rich dielectric, usually Si3N4. Although the most often adopted solution consists of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) stack, severe physical and technological constraints demand for improved device characteristics and strongly support the research for alternative material stacks.
We investigate the adoption of HfO2 as the CT layer in a TaN/Al2O3/HfO2/SiO2/Si stack. Indeed hafnium oxide was already proposed as the CT layer due to its good CMOS process compatibility and promising electrical properties, which include electron traps availability and large dielectric constant[2]. However discordant results have been reported in the literature and the correlation between material and device properties is still unclear.
In our work, the HfO2/Al2O3 stack is grown on 4.5nm thick SiO2/Si substrate by atomic layer deposition at 300°C. The HfO2 and Al2O3 films are deposited using an O3 based chemistry, while (MeCp)2Hf(Me)(OMe) and TMA are used, respectively, as Hf and Al sources. The stack physical properties are investigated as a function of film thickness and annealing temperature (Ta), which is needed for a good crystallization of the Al2O3 blocking layer. ToF-SIMS analyses revealed good thermal stability of the multilayer up to 950-1000°C, whereas diffusion phenomena take place at higher temperatures.
The electrical properties of the memory stack are measured on large area capacitors, and correlated to the structural and chemical properties. Similarly to the physical properties, the device programming, erase and retention performances are characterized as a function of Ta and of the HfO2 layer thickness (tCT). An increase in Ta generally improves the programming efficiency for fast programming pulses, possibly due to a better performance of the fully crystallized Al2O3 blocking layer. However, high Ta values are also found to degrade retention, which can be related to material inter-diffusion in the stack and indicates that a careful choice of Ta is fundamental for device optimization. On the other hand, a variation of tCT in the 12-18 nm range, weakly affects programming performances, but can be effectively used to control the erase performances. Finally, the performance of HfO2 based CT memory devices are compared with standard TANOS stack of similar equivalent oxide thickness. The use of HfO2 films as the charge trapping layer instead of Si3N4 improves the gate sensitivity factor in the 15-18 V range, which is attractive for multilevel programming, and leads to longer retention, which supports the interest of HfO2-based CT memory for high-reliability applications.
[1] C. H. Lee et al., IEDM Tech. Dig., 613-616, 2003
[2] Y.-N. Tan et al., IEEE Trans. on Electron Dev., 51, 1143 (2004)
3:30 PM - G2.3
The Characterization of the Charge Trapping Device With TiO2 Charge Storage Layer.
Dong Seog Eun 1 , Sharon Cui 1 , Tso-Ping Ma 1
1 Electrical Engineering, Yale University, New Haven, Connecticut, United States
Show AbstractCharge-trapping flash memory devices using TiO2 as the charge storage layer have been studied. The mechanisms of charge trapping/detrapping in TiO2, as well as program/erase operations for devices with TiO2 as the charge storage layer, along with memory retention characteristics, and memory endurance are also investigated. The high dielectric constant, high trapping density, and small band gap of TiO2 make fast program-erase operations possible, suggesting that TiO2 is a promising candidate for the charge storage layer.
4:00 PM - G2: Flash
BREAK
G3: MRAM I
Session Chairs
Yoshihisa Fujisaki
Bin Liu
Monday PM, April 05, 2010
Room 2011 (Moscone West)
4:30 PM - G3.1
Fabrication of 20nm Gap Magnetic Coupled Spin-torque Devices for Non-volatile Logic Applications.
Larkhoon Leem 1 , James Harris 1
1 , Stanford University, Menlo Park, California, United States
Show AbstractPower consumption in logic device has become the key design constraint in modern electronics since the proportional scaling law no longer applies to the device power consumption at the physical limits of CMOS technology. This calls for new device concepts such as Spintronics devices which are fundamentally different from CMOS. However, the MOSFET-type Spintronics transistor has not been demonstrated in experiments due to the technical difficulties in transporting and detecting spin information. In this paper, we present an alternative Spintronics logic device, Magnetic Coupled Spin-torque Device (MCSTD), which is a collective system of interacting three magnetic tunnel junctions. This device is free from spin-injection, transport and detection problems, which is different from other Spintronics transistors. It leverages spin torque transfer effect and magnetic coupling between spin-torque devices to modulate its magnetization reversal energy barrier. In MCSTDs, magnetic tunnel junctions (MTJs) are placed in the proximity of a few tens of nm, where magnetic fringing fields emanated from component magnetic devices are strong enough (> 10 Oersted) to modulate the switching characteristics of neighboring MTJs. By using two MTJs at the sides as biasing dots, four different combinations of net magnetic fields at the center MTJ are generated depending on the input spin current. This enables two-input NAND, NOR and NOT operations in this device. When compared with an ordinary single MTJ (without biasing input MTJs), MCSTD has faster switching speed at a lower energy consumption. This comes from the interaction among MTJs in MCSTD, which achieves the 30~40% reduction in the threshold switching current density. Interaction among the components in MCSTD directs the internal fringing magnetic fields to effectively lower the energy barrier. MCSTD makes a good example where collaborative collective system can be more power-efficient than a single monolithic system. In addition, non-volatility of MCSTD opens up very unique potential applications in future logic application, power management techniques and smart sensor technologies. For example, MCSTDs can replace SRAMs and pass gate transistors in reconfigurable logics such as Field Programmable Gate Array (FPGA). Instant-on/off nature of MCSTD enables low overhead system-level power gating scheme for embedded devices. Also, MCSTD can be used as magnetic sensor with in-situ logic operations for error-resilient DNA microarray applications. Finally, the fabrication process of MCSTD prototype device is described. New e-beam lithography with Chrome mask technique is developed to achieve a narrow spacing between MTJs less than 20 nm. Optimum ion-milling angle and process time for maximum etching depth with minimum redeposition rate are investigated. Switching speed modulation capability in the MCSTD that enables logic operations in the device is successfully demonstrated in experiments.
4:45 PM - G3.2
Structural, Magnetic and Magneto-tranport Properties of Reactive-sputtered Fe3O4 Thin Films.
Xinghua Wang 1 , Peng Ren 1 , Wen Siang Lew 1
1 Physics and Applied Physics, School of Physical and Mathematical Sciences, Nanyang Technological University, 21 Nanyang Link,Singapore, 637371 Singapore
Show Abstract Fe3O4 thin film is an interesting spintronic[1] material because of its full negative spin polorization, and high curie temperature (858K)[2] properties. The half matellic property of Fe3O4 also makes it compatible with semiconductors as the conductivity mismatch issue[3] can be minimised. In this work, we have grown 60-nm-thick Fe3O4 films on SiO2(300 nm)/Si substrates at room temperature(RT) and 300°C, using DC reactive magnetron sputtering techniques. A high purity Fe target (99.995%) was sputtered in Ar-O2 mixture gas flow(27:6.8). The base pressure was better than 5.0E-8 Torr and the deposition pressure was maintained at 5 mtorr. Conventional θ-2θ X-ray diffraction measurement of the films deposited at RT and 300°C show distinct Fe3O4 peaks in the (311), (511), (220) and (400) orientations. The full width at half maximum (FWHM) of the peaks of the film sputtered at 300°C are smaller, indicating a better crystallization of the film deposited at 300°C. Our SEM observations show that the grain size of the films increases from 10 nm to around 25 nm when the sputtering temperature increases from RT to 300°C which is in accordance with the conclusion drawn from the XRD measurements. Our XPS scan patterns show that the Fe 2p spectral peaks are broad and positioned at 711eV and 724 eV, with no satellite line at 719 eV. This XPS measurement confirms that the sputtered films are magnetite. Current-voltage measurements at different tempretures show that the resistivity of the films increase exponentially with decreasing temperatures, and exhibit a sharp metal-insulator transition from 90K to 120 K, indicating that the Verwey transition feature is present in the magnetite film. The Verwey transition tempreture observed in thin film differs from that in the bulk,which is possibly due to cation vacancy and nonstoichiometric deviation. The saturation magnetization Ms of the Fe3O4 film measured by vibrating sample measurement at RT is found to be 325 emu/cm3 and 430 emu/cm3, respectively,which is considerd high in magnitude. The RT magnetoresistance(MR) measurement shows that the maximum MR occurs around the coercive field. It is possibly due to the randomly oriented grains at the coercive field. We have fabricated spin-valve structures using the sputtered Fe3O4 film as the hard layer. GMR and MOKE measurement results will be presented.References[1]Y. Ohno et al, Nature, vol. 402, pp. 790-792, Dec 1999.[2]G. M. Muller et al, Nature Mater., vol. 8, pp. 56-61, Jan 2009.[3]W. B. Mi et al, Acta. Mater., vol. 55, pp. 1919-1926, Apr 2007.
5:00 PM - G3.3
Sol-gel-derived Epitaxial Nanocomposite Thin Films With Large Magnetoelectric Effect.
Bin Liu 1 , Tao Sun 1 , Jiaqing He 1 , Vinayak Dravid 1 2
1 Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois, United States, 2 International Institute of Nanotechnology, Northwestern University, Evanston, Illinois, United States
Show AbstractMultiferroic magnetoelectric (ME) materials exhibit simultaneous ferroelectric (FE) and (anti)ferro- or ferri- magnetic (FM) properties, which can be traced back to early study in the 1960s. Recent revival of research interest driven by fundamental and technological aspirations like spintronics, sensors and memory devices, has resulted in remarkable progress in growth, characterization and application. Due to scarcity and weak room-temperature ME effect in single phase materials, strain-induced ME effect in heterostructures between FE phase and FM phase provides promising strategy to enhance the properties due to greater design flexibility and multifunctionality. Meanwhile, motivated by the on-chip integration in microelectronic devices, multiferroic nanocomposites have been deposited in film-on substrate geometry. Intimate contact between two phases and small clamping effect from the substrate are crucial. Epitaxial multiferroic nanocomposite films are exclusively grown by delicate vacuum deposition methods. However, high cost and complexity of necessary equipments and restriction of coating areas limits their applications. Meanwhile, sol-gel processes, providing advantages like easy set-up, flexible control of stoichiometry, low cost and large-area coating, have been developed for over 60 years, and used to prepare various functional films like nonvolatile ferroelectric memories. However, epitaxial composite thin film is often precluded by its complicated chemistry and nucleation/growth mechanisms.Here, we report successful synthesis of sol-gel derived epitaxial multiferroic nanocomposite thin films on commensurate single crystal substrates, and report large ME effect with sharp transition, observed in the temperature-dependent magnetization measurement. BaTiO3 (BTO) is selected as the room temperature FE phase for its lead-free environment-friendly components, while CoFe2O4 (CFO) as the FM phase due to its large magnetostriction and high Curie temperature. Analytical electron microscopy techniques including Z-contrast images and electron dispersive spectroscopy show the phase separation between BTO and CFO and the derived nanostructures. Heteroepitaxy and intimate contact between two phases are confirmed by both high resolution X-ray diffraction and high resolution electron transmission microscopy. Ferroelectric property and magnetic property of the nanocomposite thin film are studied by Ferroelectric Tester and quantum interference device magnetometry measurements, respectively. We observe large change in magnetization with sharp transition (> 50% change in 1 K step) when BTO-CFO composite thin film undergoes structural transition. We attribute this remarkable phenomenon to the combination of small clamping and the large epitaxial interface-area-to-volume ratio in the nanoparticulate structures. The presentation will cover these results and highlight opportunities for similar phenomena in nanopatterned geometries.
Symposium Organizers
Caroline Bonafos CEMES/CNRS
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Panagiotis Dimitrakis NCSR "Demokritos"
G4: Organic I
Session Chairs
Panagiotis Dimitrakis
En-Tang Kang
Sashi Paul
Tuesday AM, April 06, 2010
Room 2011 (Moscone West)
10:00 AM - G4.2
Inkjet-printed Organic Non-volatile Memory Arrays Using Ferroelectric Field-effect Transistors.
Tse Nga Ng 1 , Jurgen Daniel 1 , Sanjiv Sambandan 1 , Raj Apte 1 , Ana Arias 1
1 Electronic Materials and Devices Lab, Palo Alto Research Center, Palo Alto, California, United States
Show AbstractNon-volatile memory devices for mechanically flexible electronics are being developed using organic materials to integrate data-sensing and storage. Inkjet patterning of ferroelectric field effect transistors (feFETs) was achieved with poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) as the dielectric, poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophenes) (PBTTT) as the semiconductor, and nanoparticle Ag as the electrodes. The transistor characteristics were monitored to understand the limiting factors to data retention time, and degradation in the dielectric and in the semiconductor was separated for understanding the origins of instability. We have examined the changes in semiconductor mobility m, threshold voltage VT, and dielectric capacitance Cf, with time. The measurement results indicated that shifts in VT contributed to ~55% of the loss in feFET current, while decreasing Cf, and m accounted for ~25% and ~20% of the current decay, respectively. The current decay of feFET hysteresis was dominated by charge trapping due to ferroelectric polarization. With better understanding of the interfacial effects, memory feFETs are shown to retain 50% of output current over 7 days. Finally, active-matrix arrays with feFETs have been fabricated to demonstrate the addressing of individual memory cells. The inkjet-printed memory arrays were demonstrated to show less than 10% cross talk between neighboring pixels. It was found that the array uniformity was affected by variations in semiconductor mobility and charge trapping rates among the transistors. The results suggest that, in addition to improving performance of individual feFETs, achieving better array uniformity is essential for the arrays to become practical components in flexible electronic applications.
10:15 AM - G4.3
Structural, Magnetic and Magnetoresistive Properties of Organic Spin Valves With Tetraethyl Perylene Tetracarboxylate Spacer Layers.
Jean-Francois Bobo 1 , Benedicte Warot-Fonrose 2 , Christina Villeneuve 3 , Elena Bedel 3 , Isabelle Seguy 3
1 NMH-ONERA, CEMES-CNRS, Toulouse France, 2 nMat, CEMES-CNRS, Toulouse France, 3 LAAS, CNRS, Toulouse France
Show AbstractWe have prepared spin valves with a perylene derivative, PTCTE (PTCTE: tetraethyl perylene 3, 4, 9, 10-tetracarboxylate) spacer layer and transition metal ferromagnetic electrodes (NiFe and Co).Organic spintronics has been of high interest for several years since the discovery of magnetoresistance in manganite and Alq3 or T6 based structures. Such structures may open the path to a new generation of organic sensors, memories and other devices. Perylene molecules are traditionally used as electron transport materials in optoelectronic devices like OLED (organic electroluminescent diodes) and solar cells. These molecules have not yet been used in organic spintronic devices.NiFe/PTCTE/Co devices were prepared by dc sputtering for the electrodes (with direct or off-axis sample configuration for the upper electrode), and vacuum sublimation for the organic layer. No insulating tunnel barrier was used in these structures. We show that on-axis cobalt deposition of the top electrode causes damages on the PTCTE layer, inducing low resistance or shorted devices. On the contrary, off-axis cobalt deposition preserves the integrity of the PTCTE layer and leads to functional organic magnetoresistive devices.CPP (current perpendicular to plane) devices geometry was obtained with millimetric contact masks determining a CPP spin valve area of 1 mm x 1 mm. Up to now, our best samples have a spin valve magnetic behavior and exhibit up to 3% MR response at low temperature for a 300 nm organic spacer layer. This is one of the highest reported value of magnetoresistance for such an organic spacer thickness. It suggests a spin diffusion length in PTCTE in excess of 100 nm. We will give detailed review of our recent results, including the dependence of magnetoresistance with spacer layer thickness, the applied voltage and temperature. We will also present recent results of atomic force microscopy (AFM) for films morphology, conductive tip AFM for the investigation of inhomogeneity of current distribution, electron microscopy and electron energy loss imaging for interface chemical profiling. Finally, we will give an estimate of the spin relaxation time in PTCTE thanks to measurements of electron mobility by time-of-flight technique.
10:30 AM - G4.4
Tunable Injection Barrier in Organic Resistive Switches Based on Phase Separated Ferroelectric-semiconductor Blends.
Kamal Asadi 1 , Tom de Boer 1 , Paul Blom 1 3 , Dago de Leeuw 1 2
1 Physics of Organic Semiconductors, University of Groningen, Groningen Netherlands, 3 , Holst Center, Eindhoven Netherlands, 2 , Philips Research Labs, Eindhoven Netherlands
Show AbstractWe fabricate organic non-volatile resistive bistable diodes based on phase separated blends of ferroelectric and semiconducting polymers. The polarization field of the ferroelectric modulates the injection barrier at the semiconductor-electrode contact and, hence, the resistance of comprising diodes. Comparison between the on- and off current of switching diodes, with the current measured for semiconductor-only diodes reveals that the switching occurs between bulk limited, i.e. space charge limited, and injection limited current transport. By deliberately varying the HOMO energy of the semiconductor and the work-function of the metal electrode, we demonstrate that injection barriers up to 1.6 eV can be surmounted by the ferroelectric polarization yielding on/off current modulations of more than five orders of magnitude. We rationalize the exponential dependence of the current modulation, with a slope of 0.25 eV/decade, on the magnitude of the injection barrier. Bistable Schottky diodes with high on/off current modulation ratio are demonstrated and integration into a memory array is discussed.
10:45 AM - G4.5
Resistive Switching Memory Based on Solid Polymer Electrolytes.
Tohru Tsuruoka 1 , Shouming Wu 1 , Kazuya Terabe 1 , Tsuyoshi Hasegawa 1 , Jonathan Hill 1 , Katsuhiko Ariga 1 , Masakazu Aono 1
1 , National Institute for Materials Science, Tsukuba Japan
Show AbstractNonvolatile resistive switching memory is one of the most attractive alternatives to the current memory technologies such as Flash and dynamic random access memories. Among various types of nonvolatile memories, cation-migration-based resistive switching cells are especially attractive, because of a high scalability and low power consumption. These cells are composed of a simple MIM structure, in which an inorganic solid electrolyte such as Ag2S, Cu2S, and GeSe, is sandwiched between an electrochemical active electrode (usually Ag or Cu) and an inert metal electrode like Pt. Here, we demonstrate that the resistive switching memory can be realized using an Ag-ion-conductive solid polymer electrolyte (SPE), based on the cation transport. Simple Ag/SPE/Pt structures with a polyethylene oxide – silver perchlorate complexes film showed bipolar resistive switching under bias voltage sweeping. This switching behavior was dependent on the silver perchlorate concentration. From thermal, electrical, and electrochemical measurements for the SPE films, we concluded that the observed switching results from formation and dissolution of a silver filament inside the SPE film by electrochemical reactions. The device also exhibited high off/on resistance ratios, high programming speeds, and long retention properties. These results suggest that SPE-based resistive switches may be suited for flexible nonvolatile memory applications.
11:00 AM - G4: Organic
BREAK
11:30 AM - G4.6
Rewritable Switching Operation of 1 Diode-1 Resistor for Organic Memory Devices.
Byungjin Cho 1 , Tae-Wook Kim 1 , Sunghoon Song 1 , Yongsung Ji 1 , Minseok Jo 1 , Hyunsang Hwang 1 , Gun-Young Jung 1 , Takhee Lee 1
1 Department of Nanobio Materials and Electronics, Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju , Cheolanam-Do, Korea (the Republic of)
Show AbstractCross-talk interference between memory cells can occur due to leakage current paths (called sneak paths) through neighbouring cells with low resistances in cross-point array structures [1] or an excess of current that may induce electrical damage [2]. This phenomenon disturbs reading process of the selected cell, which must be absolutely eliminated to enable practical memory application. International Technology Roadmap for Semiconductors (ITRS) suggested that the combination of a diode or transistor with a resistor in a single chip is indispensable for the prevention of this undesired cross-talk [3]. The architecture of one diode and one resistor (1D-1R) [4] or one transistor and one resistor (1T-1R) [5] can improve reading accessibility in an integrated memory array structure. Particularly, the 1D-1R architecture is preferred in terms of integration because it occupies less area. Furthermore, the design and fabrication of 1D-1R devices are simpler than for 1T-1R devices.Here, we report on the development of one-diode and one-resistor (1D-1R) hybrid-type devices consisting of inorganic Schottky diodes and organic unipolar memory, demonstrating electrically rewritable switching in the 1D-1R system [6]. The 1D-1R array architecture improves the sensing efficiency of the array memory cell, ultimately creating the possibility for high-density integrated organic memory devices without restrictions due to cross-talk between cells.Reference[1]M.-J. Lee et al, Adv. Mater. 2007, 19, 3919.[2]K. Kinoshita et al, Appl. Phys. Lett. 2008, 93, 033506.[3]International Technology Roadmap for Semiconductors, ITRS, 2007, http://www.itrs.net/Links/2007ITRS/Home2007.htm[4]M.-J. Lee et al, Adv. Funct. Mater. 2008, 18, 1.[5]T.-W. Kim et al, Adv. Mater. 2009, 21, 2497.[6]B. Cho et al, Adv. Mater. 2009, accepted.Acknowledgements: National Research Laboratory (NRL) program from the Korean Ministry of Education, Science and Technology (MEST), the Program for Integrated Molecular System at GIST, and the SystemIC2010 project of the Korea Ministry of Knowledge Economy.
11:45 AM - G4.7
Study on C60 Doped PMMA for Organic Memory Devices.
Micael Charbonneau 1 , Raluca Tiron 1 , Julien Buckley 1 , Mathieu Py 1 , Jean Paul Barnes 1 , Samir Derrough 1 , Gerard Ghibaudo 2 , Barbara De Salvo 1
1 Nanotec Division/ Advanced Memory Technologies Laboratory, CEA LETI MINATEC, Grenoble France, 2 , IMEP-LAHC, CNRS, MINATEC, Grenoble France
Show AbstractThe motivation of this study is to investigate the potential of doped polymeric resist as active layer in future memory applications. Indeed, this class of organic materials could combine electrical memory effects such as charge trapping or resistive bistability brought by dopant inclusions with respect to thermal and mechanical properties of the polymeric matrix as well as a high potential in terms of scalability from direct patterning by lithography. Until now, several compositions with both inorganic and organic doping have been presented from an electrical point of view but few of them deal with the final material and thin film properties. In this work we present material and electrical characterizations of thin film PMMA insulating polymer resist doped with C60 Buckminster fullerenes.First we focus on physical chemical material characterization in order to quantify C60 loading rate and dispersion within the polymer matrix. Thermal analysis consisting of Thermal Gravimetric Analysis (TGA) and Differential Scanning Calorimetry (DSC) were performed to monitor the impact of C60 dopant on resist properties. Thus we demonstrate that there is no modification of material glass transition temperature with C60 loading rate. However, we show that the amplitude of the heat capacity (ΔCp) depends on C60 concentration and may be used in order to quantify C60 dopant in the resist matrix. This quantification method was successfully confirmed by Tof-SIMS measurements. In parallel, as the employed polymer, PMMA, is also a well known ebeam positive resist, we investigated the patterning capabilities of PMMA/ C60 blends. In this context E-beam exposure tests were carried out on un-doped and doped PMMA samples to investigate material processability in terms of resolution, roughness and sensitivity. Thus we show that the patterning properties of PMMA could be of high potential as a scaled active layer for future memory devices.Finally, to investigate both charge trapping and resistive bistability effects induced by C60 acceptor molecule doping, Metal-Insulator-Silicon (MIS) and Metal-Insulator-Metal (MIM) structures were fabricated via spin-coating and metal evaporation. To carry out a complete and critical study of the impact of material compositions on device characteristics different materials were used: different C60 loading rates (0 to 50 %) as well as oxidizible or non oxidizible electrodes (Pt, Au, Al…).
12:00 PM - G4.8
Au Nanoparticle-Poly(N-vinylcarbazole) Colloids Hybrid Layer-based Flexible Nonvolatile Bistable Organic Memory (BOM).
Won Kook Choi 1 , Dong-Ik Son 1 , Dong-Hee Park 1
1 Thin Film Material Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of)
Show AbstractWe report on the non-volatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles embedded in a conducting poly N-vinylcarbazole (PVK) colloids hybrid layer deposited on flexible polyethylene terephthalate (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. Current-voltage (I-V) measurements on the Al/[Au nanoparticles (NPs) embedded in a conducting PVK polymer layer]/ITO/PET sheet structures at 300 K showed non-volatile electrical bistability behavior. A clockwise C-V hysteresis curve indicates a hole as a net charge carrier and the average induced charge on Au nanoparticles was quite large, as much as 5 holes/NP at a sweeping voltage of 3 V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as 1×10e5, a value almost the same as that of devices fabricated on a glass substrate. The cycling endurance tests of the ON/OFF switching for the BOM devices exhibited a high endurance of above 1.5×10e5 cycles and a high ON/OFF ratio of 10e5 could be achieved consistently even after quite a long retention time of more than 1x106 s. The memory mechanism of the fabricated BOM device is described on the basis of the I-V results and energy level diagrams. The new intermediate states inside the band gap introduced upon the interaction between Au NPs and PVK colloids at their interface are estimated through the density of states (DOS) and projected DOS (PDOS) calculations using density functional theory (DFT). Based on both the carrier transport model and theoretical calculations using DFT, it appears that a low-conductivity state was achieved by holding a hole injection into the induced impurity levels through Child’s law and trap-charge-limited-current. It also appears that a high conductivity state was achieved by subsequent hole transportation through Fowler-Nordheim (FN) tunneling from an impurity band to Au NPs.
12:15 PM - G4.9
Enhanced Currents and Electrode Corrosion Induced by Field-absorbed Water in Cu/ P3HT/ Au Junctions.
Nikolaus Knorr 1 , Silvia Rosselli 1 , Rene Wirtz 1 , Gabriele Nelles 1
1 Materials Science Laboratory, SONY Deutschland GmbH, Stuttgart Germany
Show AbstractCu/ regiorandom Poly (3-Hexylthiophene)/ metal junctions have been reported to exhibit reliable metal-filament resistive switching properties. The filament formation mechanism has been found to include ionization of the Cu electrode and Cu ion drift within the P3HT layer, but no electrolyte has been identified. We have analyzed the effect of ambient humidity on current-voltage curves in Cu/ P3HT/ Au junctions before filament formation. A strong counter-clockwise hysteresis sets in at a positive threshold voltage Vth (with the bias applied to the top Au electrode), which is a function of the relative humidity (RH) and the P3HT film thickness. At 45% RH, the hysteretic current sets in at about 60 MV/ m. We have furthermore uncovered the Cu bottom electrodes after taking I/V-curves by dissolution of the P3HT layer, revealing pit corrosion and crystal formation for junctions driven to voltages above Vth. The crystals are composed of 85% Cu and 15% S, as determined by energy dispersive X-ray spectroscopy. We explain the findings by field induced water absorption in the P3HT layer forming an electrolytic cell. The results presented here further our understanding of ion conduction and metal filament formation in organic bistable devices, and may be of importance also in relatively dry conditions.
12:30 PM - G4.10
Structure, Mechanism, and Programming Sequence for Repeatable Bipolar Resistive Electrical Switching of AgTCNQ-based Memory Cells.
Robert Mueller 1 , Jan Genoe 1 , Paul Heremans 1 2
1 Large Area Electronics, IMEC v.z.w., Leuven Belgium, 2 ESAT, KULeuven, Leuven Belgium
Show AbstractResistive electrical switching memories [1] are currently investigated for non-volatile memory applications, targeting the low-cost mass storage media market as replacement of traditional silicon based Flash memories. Memory elements based on the charge-transfer salt CuTCNQ (where TCNQ denotes 7,7',8,8'-tetracyanoquinodimethane) have previously been shown to achieve up to 10000 and more write/erase (W/E) cycles [2-4]. Although AgTCNQ (the silver analogue of CuTCNQ) was reported to display resistive electrical switching in 1983 [5], corresponding memory cells are far less performing in terms of W/E cycles than with CuTCNQ. Indeed, scientific literature on AgTCNQ mostly reports preparation methods and describes typically only briefly the OFF to ON transition. Bipolar resistive electrical switching – as typical for CuTCNQ – was only reported by Tu et al. [6], with an endurance of two W/E cycles.Based on the generalized switching mechanism for solid ionic conductors (SICs, e.g. CuTCNQ) with a "switching layer" (SL) [7], and recent engineering improvements of the SIC\SL interface [4], we investigated the resistive electrical switching of AgTCNQ based memory cells with a dedicated SiO2 SL. Results showed that bipolar resistive electrical switching with more than 100 W/E cycles could be achieved for prototype n+Si\SiO2\AgTCNQ\Au memory cells, provided that the growth of the conductive channel in the ON state is controlled by using a current compliance. Switching the memory back to the OFF state required higher current intensities; keeping the same current compliance level typically prevented - and exceptionally led to time delayed - OFF switching. This unanticipated comportment, as well as an increase in conductivity just before the ON to OFF transition, are physically explained by electron transfer processes involving formation of conductive silver channels within the SiO2 "switching layer".These results constitute further evidence that bipolar resistive electrical switching of Ag+ and Cu+ solid ionic conductors such as CuTCNQ and AgTCNQ indeed implies electrochemical processes whose extent must be controlled in order to achieve highly repeatable W/E cycling as required for mass-storage applications.We gratefully acknowledge the IMEC P-Line, L. Goux, and D. J. Wouters (both IMEC v.z.w.) for providing n+Si\SiO2 wafers. This research was performed within the framework of the EMMA project of the European Commission (FP6-033751).[1] R. Waser et al., Adv. Mat. 21 (2009) 2632[2] T. Kever et al., Thin Solid Films 515 (2006) 1893[3] R. Mueller et al., Mater. Res. Soc. Symp. Proc. 997 (2007) I01-10[4] R. Mueller et al., MRS Spring Meeting 2009, talk H7.4[5] R. S. Potember et al., Synth. Met. 4 (1982) 371[6] D. Tu et al., Chin. J. Semicond. 29 (2008) 50[7] R. Mueller et al., Mater. Res. Soc. Symp. Proc. 1071 (2008) F06-04
12:45 PM - G4.11
Small Organic Molecules for Electrically Re-writable Non-volatile Polymer Memory Devices.
Iulia Salaoru 1 , S Paul 1
1 Emerging Technologies Research Centre, De Montfort University, Leicester United Kingdom
Show AbstractThe usage of organic materials in the manufacture of electronic polymer memory devices is on the rise [1,4]. Polymer memory devices are fabricated by depositing a blend (an admixture of organic polymer, small molecules and nanoparticles) between two metal electrodes. The primary aim is to produce devices that exhibit two distinct electrical conductance states when a voltage is applied. These two states can be viewed as the realisation of non-volatile memory. This is an interesting development; however, there are a number of theories that have been proposed to explain the observed electrical behaviour. We have proposed a model that is based on electric dipole formation in the polymer matrix [5 ]. Here, we investigate further the proposed model by deliberately creating electric dipoles in a polymer matrix using electron donors (8-Hydroxyquinoline, Tetrathiafulvalene and Bis(ethylenedithio)tetrathiafulvalene) and electron acceptors (7,7,8,8-Tetracyanoquinodimethane, Tetracyanoethylene and Fullerene) small molecules. Two types of structures were investigated (i) a metal/blend of polymer and small molecules/metal (MOM), device and (ii) a metal/insulator/blend of small molecules and polymer/semiconductor (MIS) architecture. A blend of polymer and small organic molecules was prepared in methanol and spin-coated onto a glass substrate marked with thin aluminium (Al) tracks ; a top Al contact was then evaporated onto the blend after drying - this resulted in a metal-organic-metal structure. The MIS structures consisted of an ohmic bottom Al contact, p-type Si, a polymer blend (two small organic molecules and insulating polymer), followed by polyvinyl acetate and finally a top, circular Al electrode. In-depth FTIR studies were carried out to understand the observed electrical behaviour. An electrical analysis of these structures was performed using an HP4140B picoammeter and an HP 4192A impedance analyser at a frequency of 1 MHz. References:[1] I.Salaoru, S.Paul, Phil.Trans.R.Soc.A, 367, 4227, (2009).[2] I.Salaoru, S.Paul, Mater.Res.Soc.Symp.Proc, 1114-G12-09, (2009),[3] I.Salaoru, S.Paul, Advances in Science and Technology 54, 486 (2008).[4] I.Salaoru, S.Paul, Journal of Advanced Materials 10(12), 3461, (2008).[5] S. Paul, IEEE, S. Paul, IEEE Transaction on Nanotechnology, (2007), 6, 191-195.
G5: ReRAM I
Session Chairs
Panagiotis Dimitrakis
Cheol Seong Hwang
Daniele Ielimini
Sabina Spiga
Tuesday PM, April 06, 2010
Room 2011 (Moscone West)
2:30 PM - **G5.1
Resistance Switching in Transition Metal Oxides for Non-volatile Memory Application.
Sabina Spiga 1
1 Laboratorio MDM, CNR-INFM, Agrate Brianza Italy
Show AbstractResistance switching Random Access non-volatile Memories (ReRAM) represent a large class of emerging non-volatile memory concepts based on a resistor as memory element that can be programmed in a high and low conductive state, using electrical pulses. These memory devices are gaining interest to overcome the limits of the current Flash technology for the 22 nm node and beyond, as well as for 3D high-density cross-bar architectures [1]. Among the investigated materials for ReRAMs, such as organic compounds, perovskite, amorphous silicon, and solid electrolytes, transition metal binary oxides offer high potential scalability, thermal stability, and can be more easily integrated in CMOS fabrication than organic materials and ternary compounds.
Oxide-based ReRAM devices exploit the functionality of metal/transition metal binary oxides/metal heterostructures: after an initial electro-forming step, which induces a current-limited electric breakdown in the pristine sample, the memory element can be reversibly switched between a low resistance set state and a high resistance reset state. Reversible switching is achieved as a conductive filament is repeatedly formed and dissolved inside the dielectric, by means of electrical pulses [2]. Although various binary oxides, such as NiO, TiO2, CuOx, HfO2, ZnO, and Nb2O5, exhibit switching properties, for their implementation in high-density ReRAM it is still mandatory: (i) to obtain a better understanding/control of the switching mechanisms down to the nano-scale; (ii) to optimize the electrical properties in terms of programming parameters, endurance and reliability; (iii) to address material selection in terms of CMOS compatibility, and control of the physical properties and oxide/metal interfaces.
In this work, after a short overview of the state of the art on transition metal binary oxides for ReRAM application, we will focus on some representative systems addressing the open issues described above and discussing into details the switching properties and mechanisms, as well as the scaling issues. We will focus first on NiO-based heterostructures, where polycrystalline NiO films are grown by atomic layer deposition and electron beam evaporation on Pt, n+-Si, Ni, TiN and W bottom electrodes [3]. NiO-based ReRAMs are initially in the high resistance state and exhibit reproducible switching after an appropriate forming stage. The resistive switching parameters are investigated as a function of electrodes, and film structural/chemical properties. Possible integration schemes based on a transistor or a diode as selector for NiO-ReRAM are proposed. Finally, the switching properties of polycrystalline ZrO2 films deposited by ALD and amorphous Nb2O5 films will be also presented and compared to NiO.
[1] R. Waser and M. Aono, Nature Materials 6, 833 (2007)[2] U. Russo et al., IEDM Tech. Dig., 775 (2007)[3] S. Spiga et al., Microelectr. Eng. 85, 2414 (2008); ECS Transaction 25(6),411 (2009)
3:00 PM - G5.2
Atomic Scale Analysis of Resistive Switch in Pt/NiO/Pt Memory Cells.
Pauline Calka 1 , Eugenie Martinez 1 , Cyril Guedj 1 , Dominique Lafond 1 , Pascale Bayle-Guillemaud 2 , Blanka Detlefs 3 , Jerome Roy 3 , Joerg Zegenhagen 3
1 MINATEC, CEA, LETI, Grenoble France, 2 SPEM, CEA, INAC, Grenoble France, 3 , European Synchrotron Radiation Facility, Grenoble France
Show AbstractResistive Random Access Memories (RRAM) are interesting candidates for next generation non-volatile memory (NVM) downscaled applications. The advantageous properties of Pt/NiO-based devices in terms of data retention, low power consumption, and multi-stacking compatibility have been reported, and the understanding of switching mechanism is critical for further device integration and optimization. Several mechanisms have been proposed to explain the resistance switching phenomenon but in all these models the microscopic origin of the bistable resistance state remains controversial. In this paper, Pt/NiO layers have been integrated into elementary resistors showing stable and non-volatile switching properties which have been investigated at the atomic scale using UPS, HAXPES, and HRTEM measurements combined with atomic-scale simulations.Investigation of chemical states with depth sensitivity was performed in a non destructive way using hard x-ray photoemission spectroscopy (HAXPES). Measurements were carried out at the ID32 beamline of the European Synchrotron Radiation Facility (ESRF) on a ~25 nm –thick NiO layer deposited on Pt. By tuning the X-rays energy between 2.1 and 9.75 keV, the bulk and interface properties were probed non-destructively, with an overall energy resolution varying from 0.27 to 0.71 eV. Ni2p, Pt4f and O1s lines were analyzed in both the high and low resistance states to investigate chemical bindings.Results highlight an additional component related to the Ni metallic state at the Pt/NiO bottom interface for the as-deposited NiO layer. After electrical switching, an increase of the O-Ni3+ bonds at the NiO surface is observed. XPS spectra are compared in both ON and OFF states and the shifts of the C1s peak reveal the presence of positively charged species compatible with vacancy states.Complementary insight is provided by High-Resolution Transmission Electron Microscopy cross-sectional images. In the OFF state, the images demonstrate the presence of an epitaxial relationship between Pt and NiO with misorientation accommodated by misfit dislocations. Various defects are observed in the bulk NiO and at the interfaces, and local crystalline distortions are evidenced and modelled at the atomic scale. In the ON state, some possible conduction pathways are evidenced, and their shape and size are investigated. Asymmetrical dentritic alignments of defects are observed and correlated to rhombohedral distortions and combinations of twins. All these results are combined to propose a general atomic-scale model for the resistive switching in Pt/NiO/Pt memory cells. From a device point of view, the control of interfacial properties, like oxygen vacancy concentrations at the sub-nanometric scale appears to be really critical to control and optimize the switching properties. More generally, vacancy engineering is certainly a key issue to increase resistive memory performances.
3:15 PM - G5.3
Size-dependent Temperature Instability in NiO–based Resistive Switching Memory.
Daniele Ielmini 1 , Federico Nardi 1 , Carlo Cagli 1 , Andrea Lacaita 1
1 Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, MI, Italy
Show AbstractResistive switching memory (RRAM) devices are attracting a strong interest as novel nonvolatile memories for high-density storage. These memories rely on the electrically-induced insulator-metal transition in transition metal oxides, such as NiO [1], Cu2O [2] and TiO2 [3]. NiO memory display a unipolar resistance switching behavior, where the set transition (from high to low resistance) is triggered by electrical threshold switching and reduction of the oxide phase [4], while the reset transition is interpreted as thermal oxidation induced by Joule heating [5]. It was demonstrated that the resistance change is localized at a conductive filament (CF), which raises several concerns regarding the reset current scalability and the unstable metallic phase.This work addresses the reliability of unipolar RRAMs based on NiO, as a function of the size of the metallic CF responsible for the low resistance state. We varied the CF size in the memory by different reset voltage, obtaining a full spectrum of CF conduction type (metallic, semiconductor) and size. The CF area A was estimated by an Arrhenius conduction model, namely R = rho*t*exp(Ea/kT)/A, where R is the CF resistance, rho is the metallic resistivity, t is the NiO thickness and Ea is the measured activation energy for conduction. The stability of the metallic CF was studied under temperature-accelerated experiments (240-350°C), monitoring the increase of resistance with time as a result of Ni oxidation in the CF. An activation energy of 1.2 eV was found for oxidation. Most importantly, the oxidation time tau was found to decrease for increasing resistance, hence decreasing A. These data are explained by a reaction-diffusion model, which predicts that tau is proportional to A at a given T. These results suggest that, to improve data retention in NiO RRAM, the CF size should be maximized. However, this degrades the reset current, which is needed to thermally oxidize the metallic CF and is approximately proportional to A. The fundamental tradeoff between data retention and reset current can only be solved by accurate material engineering, e.g. increasing the activation energy of the solid-state oxidation to improve data retention time at smaller reset voltage and current. Other possible guidelines for material engineering to improve RRAM characteristics are discussed. These new experimental and theoretical findings represent a solid contribution to assess the feasibility and reliability of NiO RRAMs as next high-density nonvolatile memory solution.[1] I. G. Baek, et al., IEDM Tech. Dig. 587 (2004).[2] A. Chen, et al., IEDM Tech. Dig. 746 (2005).[3] D. Strukov, et al., Nature 453, 80 (2008).[4] D. Ielmini, et al., Appl. Phys. Lett. 94, 063511 (2009).[5] U. Russo, et al., IEEE Trans. Electron Devices 56, 186-192 (2009).
3:30 PM - G5.4
Oxidation Kinetics of Ni Thin Films: Application to NiO-based ReRAM.
Judit Lisoni 1 2 , Ludovic Goux 2 , Nico Jossart 2 , Malgorzata Jurczak 2 , Dirk Wouters 2
1 Physics Dptm., FCFM, Universidad de Chile, Santiago Chile, 2 , IMEC, Leuven Belgium
Show AbstractWe investigated the oxidation behavior of Ni layers, and in particular compared the oxidation behavior of 20 nm and 100 nm Ni thin films. The obtained NiOx films were incorporated as the active memory element in Ti\TiN\Ni\NiO\Ni Resistive RAM structures, and the NiOx formation parameters were correlated to the switching characteristics of the NiOx films.From the oxidation kinetics viewpoint, we found that while the oxide growth rate of 100 nm thick Ni films follows parabolic time dependence, oxidation of 20 nm Ni films tends to be linear, pointing out different mechanisms involved in the formation of the NiOx. Contrary to what is expected, annealing of the Ni films done in inert atmosphere prior to the oxidation experiments (preanneal) do not have a major influence in the oxidation curves aforementioned for both thickness cases. Moreover, there is no variation of the NiOx composition (Ni:O~0.74) for all oxidation conditions tested. On the other hand, the differences in NiOx growth mechanisms clearly link to the microstructure of the NiOx: while NiOx films growth from the oxidation of 100 nm Ni films can be rough and quite inhomogeneous in thickness (20-140 nm) the NiOx films obtained from 20 nm Ni films are quite smooth with a tight variation in thickness (25-45 nm). Moreover, no presence of voids and cracks are observed in the NiOx films grown from the 20 nm Ni films contrary to what was normally observed for the case of oxidized 100 nm Ni films. The switching behavior of the samples was very interesting. For both cases -20 and 100 nm oxidized Ni films- the switching evolves from bipolar for short oxidation time conditions to unipolar for long oxidation times. Bipolar behavior was correlated with low initial resistance values (102-103 ohm at 0.1 V) while unipolar was obtained for high initial resistance values (>104 ohm at 0.1 V). In the case of 100 nm Ni films, an anneal in inert atmosphere prior to the oxidation experiments (preanneal) favors the formation of a NiOx with a very reproducible bipolar switching; while Ni films with no preanneal show only stable unipolar switching. Differently, for the case of NiOx films obtained from 20nm Ni films, we did not observe major influence of the Ni preconditions on the switching behavior of the NiOx, however samples with preanneal do tend to have a better reproducibility of the switching events. We also observed that for the longer oxidation times the Reset operation was difficult for the case of the NiOx formed from Ni 20 nm films, contrary to what is observed in oxidized 100 nm Ni films. This can be related to the lack of adhesion between the NiOx and the TiN and the formation of a thin TiOx at the TiN top surface for the longer-oxidized 20 nm Ni films; the formation of the titanium oxide was never observed for the case of 100 nm Ni oxidized films.Partial financial support was provided to J.L. through project FONDECYT 1090332.
3:45 PM - G5.5
Correlation Between Oxygen Composition and Electrical Properties in NiO Thin Films for Resistive Random Access Memory.
Yusuke Nishi 1 , Tatsuya Iwata 1 , Tsunenobu Kimoto 1
1 , Kyoto University, Kyoto Japan
Show AbstractResistive random access memory (ReRAM) consisting of a transition metal oxide is one of the promising simple devices for a new-generation nonvolatile memory. However, fundamental properties of the oxides and their switching mechanisms have not been fully understood yet. In this study, admittance spectroscopy has been performed on nickel oxide (NiO) films with various oxygen compositions in order to characterize localized states. Impacts of the oxygen composition on the switching characteristics have also been investigated. NiO films were deposited on n-Si substrates by a reactive RF sputtering method at substrate temperature of 300C. The ratio of O2 flow rate in the Ar + O2 gas mixture was varied in the range from 3% to 20% to change the oxygen composition. The thickness of NiO was 200 to 400 nm. The oxygen composition x of NiOx films was determined as 1.0 to 1.2 (metal deficient p-type semiconductor) by RBS and EDX. Pt electrodes as ohmic contacts with a 300 μm diameter were deposited by electron beam evaporation through a metal mask. From C-V measurements of p-NiO/n-Si heterojunctions, the net acceptor concentration of NiO was estimated to be in the 10^18 cm^-3 range. Admittance spectroscopy on the p-NiO_1.07/n-Si structure revealed a clear G/w peak (G: conductance, w: angular frequency), indicating the existence of high density localized states. Based on the Arrhenius plots of emission time constants, the level (hole trap) is energetically located at 170 meV above the valence band edge. It should be noted that this value (170 meV) is similar to the activation energy obtained from the temperature dependency of resistance in the high-resistance state with the Pt/NiO_1.07/Pt stack structure. Therefore the band conduction may be dominant due to holes thermally excited from the localized levels above 300K. From the frequency dependence of capacitance, the ratio of the concentration of hole traps to that of shallow acceptors can be estimated as over 2, indicating a highly compensated material. The resistance in the high-resistance state tends to decrease with increase in the oxygen composition of NiOx (x=1.05-1.2). The detailed correlation between the resistance and the oxygen composition will be discussed. The Pt/NiOx/Pt structures were prepared to assess the switching characteristics. Among various oxygen compositions, the Pt/NiO_1.07/Pt structure exhibited stable resistance switching characteristics at temperature as high as 550K. Although the resistance ratio (HRS/LRS) decreased with temperature, the ratio was sufficiently high, 40 at 550K. This result suggests that the NiO-based ReRAM shows promise for high-temperature applications. Impacts of the oxygen composition on the switching characteristics will be discussed.
4:00 PM - G5: ReRAM
BREAK
4:30 PM - G5.6
The Effect of Ion-implantation on the Forming and Resistive Switching Response of NiO Thin-films.
Muhammad Saleh 1 , Sung Kim 1 , Dinesh Venkatachalam 1 , Kidane Belay 1 , Robert Elliman 1
1 Electronic Materials Engineering, Australian National University, Canberra, Australian Capital Territory, Australia
Show AbstractResistive switching in NiO thin-films is believed to result from thermo-chemical disruption (reset) and re-forming (set) of a conductive filament initially produced by field-induced ‘breakdown’ of the film. The latter involves the direct field-induced generation of defects and their accumulation to a threshold concentration (percolation threshold) that allows current flow through the film. By limiting the resulting current it is possible to produce a conductive path (filament) through the film without permanently damaging it (hard breakdown). Based on these mechanisms, the formation of conductive filaments and their subsequent set/reset behaviour is expected to depend on film microstructure, including the presence of grain–boundaries, residual defect concentrations and film stoichiometry (known to affect the resistivity of NiO films). Ion-implantation can be used to control each of these parameters and is therefore ideally suited to studying such dependencies. In this study, we compare the forming voltage and switching characteristics of Pt/NiO/Pt metal-insulator-metal (MIM) structures before and after implantation with Ni- and/or O- ions. Measurement are reported for samples as-implanted and after annealing at 600oC.
4:45 PM - G5.7
The Impact of Oxide Properties on Resistive RAM Electrical Characteristics.
Vincent Jousseaume 1 , Cyril Guedj 1 , Jean Francois Nodin 1 , Alain Persico 1 , Helene Feldis 2 , Stephane Minoret 1 , Anne Roule 1 , Helen Grampeix 1 , Aziz Zenasni 1 , Andrea Fantini 1 , Luca Perniola 1 , Patrice Gonon 3 , Christophe Vallee 3 , Geoffroy Auvert 2 , Jean Paul Barnes 1 , Eugenie Martinez 1 , Pauline Calka 1 , Sylvie Favier 2 , Julien Buckley 1 , Barbara De Salvo 1
1 , CEA-LETI-MINATEC, Grenoble France, 2 , STMicroelectronics, Grenoble France, 3 , LTM, Grenoble France
Show AbstractResistive Random Access Memories (RRAM) has attracted great interest for potential applications in next generation nonvolatile memory. Compared with other nonvolatile memories, they potentially offer high performances coupled to a simpler fabrication process [1-4]. Up till now, the mechanisms at the origin of the resistive switching are still the object of much controversy. Thus, key points such as material selection, material characteristics and stack (electrode, multilayer) are more important than the integration scheme and are still the hot topics in RRAM research. This paper is focused on the study of the impact of the oxide material on the resistive switching properties. Nickel oxide (NiO) which is one of the most studied materials for RRAM, is compared to Hafnium oxide (HfO2) which is usually used as a high k dielectric in advanced metal gates. Different deposition techniques (metal sputtering followed by thermal oxidation, reactive sputtering, atomic layer deposition) and the impact of several material parameters (film thickness, roughness impact, composition) were studied in order to identify the main parameters influencing the resistive switching. For theses studies, platinum was used for the top and bottom electrodes.Integrated memory cells were fabricated at the metal 1 using 200 mm backend-of-line compatible processes. We were able to obtain integrated resistors in the range 300 nm to several mm in diameter.Electrical characterization (mainly I-V characteristics), were carried out in order to study in detail the switching mechanisms. It is shown that both nickel oxide and hafnium oxide can present non-polar switching behaviour. It means that a SET can be obtained in a given polarity and a RESET can be performed in the same polarity or in the opposite one. The interpretation of our electrical results are consistent with the filamentary model usually proposed in the literature [1] and our experiments highlight the impact of material properties (composition, film thickness, roughness, deposition technique) on the RRAM parameters (SET and RESET voltage, reset current, On and OFF resistance, …). The importance of the electrical methodology test is also detailed. In conclusion, this work shows important information in order to improve the understanding of the switching mechanisms in RRAM and proposes pathways for the development of integrated devices. [1] A. Sawa, Materials Today, 11 (2008) 28. [2] I.G. Baek et al, proccedings of IEDM (2005) 750.[3] Y. Sato et al, IEEE Transactions On Electron Devices, 55 (2008), 1185.[4] Z. Wei et al, proccedings of IEDM (2008) 4796676.
5:00 PM - G5.8
Time-dependent Switching in HfO2 RRAM.
Christophe Vallee 1 , Patrice Gonon 1 , Vincent Jousseaume 2 , Helene Grampeix 2
1 LTM, UJF, Grenoble France, 2 LETI, CEA,MINATEC, Grenoble France
Show AbstractResistive switching is a phenomenon by which some electrical insulators display a change of resistance upon application of a bias voltage. Recently this phenomenon has attracted considerable interest for the fabrication of nonvolatile Resistive Random Access Memories (RRAMs) [1]. In the last years, oxide-RRAMs based on conventional insulators already developed for MOS or MIM capacitors have been tested. The choice made here is to elaborate HfO2-RRAM cells. This was based on the fact that hafnia-based dielectrics were the most promising materials for the manufacturing of CMOS gates below the 45 nm technology node. Therefore, as far as integration and process compatibility are concerned, HfO2 would be an interesting candidate. The dielectric is deposited by ALD (Atomic Layer Deposition) with different materials as bottom and top electrodes.Electrical characterizations were performed on blanket films. HfO2-based Resistive Random Access Memories were studied in both voltage sweep mode and constant voltage stress (CVs) mode. In voltage sweep mode we obtain bipolar devices without forming on contrary to results obtained by Walczyk et al [2]. Electrical measurements are correlated to chemical analysis results (XPS, ATR and FUV-SE), with special attention devoted to metal/oxide interface investigations. It is shown that the ratio between the resistance in the ON state and in the OFF state strongly depends on the nature of the top and bottom electrode. Role of oxygen vacancies accumulation near the cathode/HfO2 interface, resulting on a Schottky barrier width narrowing and an electron injection by tunneling is discussed.In CVs mode, HfO2-based RRAMs are able to switch below Vset which is usually measured in a sweep mode and shows a unipolar behaviour. In that sense they are similar to PCRAMs [3,4] and CBRAMs [5] where identical phenomena have been reported. More generally, such a behavior is reminiscent of metallic dendrites growth in electrolytes [6,7]. From a practical point of view, such "sub threshold" switching may adversely affect RRAMs operation if the voltage is not strictly controlled. The behaviour reported here in HfO2-RRAMs is believed to be observable in other oxide-based RRAMs. [1] R. Waser et al, Nature Materials 6, 833 - 840 (2007). [2] Ch. Walczyk et al, J. Appl. Phys. 105, 114103 (2009). [3] I. V. Karpov et al, Appl. Phys. Lett. 92, 173501 (2008). [4] V.G. Karpov et al, J. Appl. Phys. 104, 054507 (2008). [5] Sung Hyun et al, Nano Lett. 9, 496 (2009). [6] J. L. Barton et al, Proc. R. Soc. Lond. A 268, 485 (1962). [7] C. Monroe et al, J. Electrochem. Soc. 150, A1377 (2003)
5:15 PM - G5.9
Conductive AFM Studies of Morphological and Electrical Changes in Transition Metal Oxide Memristive Devices Induced by Electroforming and Switching.
Ruth Muenstermann 1 2 , Jianhua Yang 2 , John Paul Strachan 2 , Gilberto Medeiros-Ribeiro 2 , Ingo Krug 1 , Regina Dittmann 1 , Rainer Waser 1
1 Institute of Solid State Research, Research Center Juelich, Juelich Germany, 2 , Hewlett-Packard Labs , Palo Alto, California, United States
Show AbstractResistive switching in transition metal oxides has been studied very extensively and occurs within a wide variety of materials. The actual microscopic processes, however, are not yet completely understood. A common feature of most switching materials is the necessity of an initial electroforming step before stable resistive switching can be realized. Understanding the exact influence of this forming step as well as the influence of subsequent resistive switching on the junction and, moreover, being able to distinguish between both of them, is clearly an important prerequisite for understanding the overall switching process.We present conductive AFM studies of TiO2 and SrTiO3 memristive junctions enabled by a delamination process. By removing the top electrode while still keeping the chemical integrity of the processed devices, we were able to investigate the oxide/electrode interface and detect effects of the electroforming and switching on the local conductivity of the sample. While electroforming is related to the irreversible formation of a single, defined conducting path through the junction [1, 2], switching yields additional effects [3]. A comparison of only formed to formed and switched TiO2 samples shows that subsequent switching steps do not take place at the exact forming spot but rather next to it. They result in additional conducting structures that evolve in length with an increasing number of switching cycles. Moreover, employing the metal coated tip of the AFM as a virtual electrode we can simulate the actual switching process in SrTiO3 even after removal of the top electrode and visualize the areas of a junction involved in the switching process. Two different types of switchable areas can be found: a locally confined one showing the standard switching polarity, and a spatially distributed one exhibiting the opposite polarity. Combining PEEM and conductive AFM data we speculate on the nature of those effects.[1] J. J. Yang, F. Miao, M. D. Pickett, D. A. A. Ohlberg, D.R. Stewart, C. N. Lau, and R. S. Williams, Nanotechnology 20, 215201 (2009).[2] J.P. Strachan, J.J. Yang, R. Muenstermann, A. Scholl, G. Medeiros-Ribeiro, D.R. Stewart, R.S. Williams, Nanotechnology 20, 485701 (2009).[3] R. Muenstermann, J.J. Yang, J.P. Strachan, G. Medeiros-Ribeiro, R. Dittmann and R. Waser, submitted (2009).
5:30 PM - G5.10
Role of Oxygen Vacancy in Resistive Switching Effect of Pr1-xCaxMnO3 Junctions.
Shutaro Asanuma 1 2 , Hiroyuki Yamada 1 , Hiroshi Akoh 1 2 , Akihito Sawa 1
1 Nanoelectronics Research Institute, National institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan, 2 Core Research of Evolutional Science & Technology(CREST), Japan Science and Technology Agency (JST), Kawaguchi, Saitama, Japan
Show AbstractResistive switching (RS) effect of transition metal oxides (TMOs) has attracted great attention because it can be utilized for nonvolatile memories, i.e., resistance random access memory (ReRAM), which is a promising candidate for the next generation nonvolatile memory. From recent studies, it becomes clear that an electrochemical migration of oxygen vacancy at the interface between TMOs and metal electrode play a crucial role in RS effect. However, the impacts of oxygen vacancy on the electronic structure and/or the band diagram at the interface in the controlling the electrical conduction process have not been understood yet.In this study, we have investigated the Ca composition x dependence of resistive switching (RS) characteristics and band diagrams in Ti/Pr1-xCaxMnO3 [PCMO(x)] junctions and the impact of oxygen vacancy on the band diagrams. The RS ratio RH/RL showed the clear x dependence, where RH and RL are resistance values of high and low resistance states, respectively. The RH/RL was maximized at x ~0.4 and the Ti/PCMO(x) junctions with x > 0.8 showed almost no RS effect. The cross-sectional transmission electron microscope images of the switched Ti/PCMO(x) junctions confirmed the increase of the thickness of amorphous TiOy layers at the interfaces, which indicated that oxygen ions in PCMO(x) layer were diffused into Ti electrode due to electrochemical migration process. The electron energy loss measurements of Mn-L edge showed that the valence of Mn ions in the vicinity of the interface is smaller than that far away from the interface, indicating that oxygen-deficient layer formed in PCMO(x) at the interface. The optical absorption measurements of oxygen-deficient PCMO(x) films revealed that formation of oxygen vacancies increases the band gap of PCMO(x). The possible energetic alignments of PCMO(x) were described from the results of band gap and Fermi level measurements of PCMO(x). The possible band diagrams which were deduced from the energetic alignments indicate that the oxygen-deficient PCMO layer form in the interface of Ti/PCMO(x) junction could act as an effective barrier to the hole-carrier conduction. Based on the results, we propose that the change in the band gap of PCMO(x) at the interface, which is induced by the electrochemical migration of oxygen vacancies, accounts for the RS effect of Ti/PCMO(x) interface.
5:45 PM - G5.11
Affects of Microstructure and Oxygen Vacancy Motion on the Transport and Resistance Switching of Pt / SrTiO3-x (001) Junctions.
Wenkan Jiang 1 , Mohammad Noman 2 , Yimeng Lu 1 , James Bain 2 1 , Marek Skowronski 1 , Paul Salvador 1
1 Materials Science and Engineering, Carnegie Mellon, Pittsburgh, Pennsylvania, United States, 2 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Show AbstractElectric field induced resistance switching (or the electro-resistance effect) has been observed in a wide variety of oxides using capacitor-like structures. Oxygen vacancy motion is a commonly proposed component of the mechanism believed to be responsible for electro-resistance. However, the questions of if and how oxygen vacancy motion occurs at room temperature remain to be clarified, as well as if it truly is coupled to electro-resistance. We investigated the role of oxygen vacancy motion and microstructural features on the electro-resistance effect using Pt / single crystal SrTiO3-x(001) hetero-junctions (which are known to behave electro-resistively). Large area Pt interfaces with SrTiO3-x exhibit highly rectifying I-V characteristics in agreement with the Schottky-Mott model of a deep work-function metal in contact with an n-type semiconductor. An electron beam induced current (EBIC) study was performed on the hetero-junctions, revealing perpendicular line features aligned along the {100} directions. The contrast of the line features relative to the uniform bulk can be altered both chemically (using a low temperature air annealing) and electrically (using a voltage stress). Optical and atomic force microscopy (AFM) images taken on over-etched SrTiO3-x(001) surfaces revealed that the lines features observed in EBIC correlate with arrays of square etch pits. We fabricated various size Pt contacts, ranging from 1 µm to 200 nm in diameter, both on and off the arrays of square etch pits and measured their transport properties using conductive AFM. The EBIC data and the transport behaviors will be discussed using a model of enhanced oxygen vacancy motion along the microstructural features. It will be demonstrated that the most consistent interpretation of all observations corresponds to the redistribution of oxygen vacancies on all microstructural features, though to varying degrees. The effect of the enhanced oxygen vacancy motion on specific microstructural features on, as well as the scaling behavior of, the electro-resistance will be discussed.
G6: Poster Session: Nano-Crystal Memory II
Session Chairs
Caroline Bonafos
Panagiotis Dimitrakis
Tuesday PM, April 06, 2010
Exhibition Hall (Moscone West)
6:00 PM - G6.10
Controlling Spatial Density and Size of Metal Nanocrystals by Two-step Atomic Layer Deposition for Non-volatile Memory Applications.
Do-Joong Lee 1 , Sung-Soo Yim 1 , Ki-Su Kim 1 , Soo-Hyun Kim 2 , Ki-Bum Kim 1
1 Department of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 School of Materials Science and Engineering, Yeungnam University, Gyeongsan-si, Gyeongsangbuk-do, Korea (the Republic of)
Show AbstractNanocrystal floating-gate memory (NFGM) has been extensively researched to overcome the scaling limit of non-volatile memory devices. For the integration of NFGM, one of the important factors is the engineering of both spatial density and size of nanocrystals (NCs). To reduce a cell-to-cell deviation, it is essential to deposit NCs with the spatial density higher than 1012 cm-2. At the same time, NCs with the larger size are favorable for the better charging efficiency and the retention properties. Therefore, to optimize the performances of NFGM, it is crucial to widely control both the spatial density and the size of NCs. To deposit NCs on a tunnel dielectric, various methods including a post-annealing of physical-vapor-deposited thin films, a chemical vapor deposition, and an atomic layer deposition (ALD) have been proposed. However, these conventional methods have a critical issue that the spatial density and the size of NCs are simultaneously determined during the deposition and, consequently, the controllability is greatly limited. In this presentation, we propose a two-step ALD process for the formation of metal NCs, which has an excellent controllability and can be universally applied to any ALD systems. In this process, two deposition conditions with a different nucleation rate are combined. By rigorously controlling the amount of deposited materials during an ALD cycle, the nucleation rate of ALD-NCs could be readily modulated. The first step uses a nucleation-dominant deposition condition for the control of the spatial density, while the second step uses a growth-dominant deposition condition for the growth of the pre-deposited NCs with retarding the additional nucleation. Sequential combination of these steps can enable the extensive control of the spatial density and the size of NCs. To examine this process, we deposited Ru NCs on the Al2O3 surface using bis(ethylcyclopentadienyl)ruthenium [Ru(EtCp)2] as a precursor and O2 as a reactant. For the modulation of the nucleation rate, pulsing time and carrier flow rate of the Ru precursor were separately controlled. By sequentially combining two deposition conditions with a different nucleation rate, we could deposit Ru NCs with a wide range of the spatial density from 7.9×1011 to 3.2×1012 cm-2 and the average diameter from 1.9 to 3.3 nm. Detailed features including the morphology, spatial density, and size of Ru NCs deposited by the two-step ALD process will be presented.
6:00 PM - G6.11
MOCVD Al Nanocrystal Embedded in AlN Thin Film for Nonvolatile Memory.
Nian-Huei Chen 1 , Chiu-Yen Wang 2 , Shu-Jen Huang 3 , Fon-Shan Huang 1
1 Institute electronic engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 3 Department of Cosmetic Science and Application, Lan Yang Institute of Technology, Yilan Taiwan
Show AbstractThe use of a floating gate composed of distributed nanocrystal (NC) in the dielectric reduces the problems of charge loss encountered in conventional poly-Si thin film as floating gate and small change in flat band voltage for SONOS structure due to small number of trap sites in Si3N4. The metal NC memory has exhibited several advantages, such as as stronger coupling with the conduction channel and higher density state around of Fermi level. Furthermore, utilizing high-k material as an alternative tunnel and control dielectric makes flash memory more scalable.In this work, a simple RTA-MOCVD system is utilized to deposit AlN/Al-rich AlN/AlN layered structure on Si wafer without breaking vacuum. The AlN thin film with wide band gap of 6.2eV is used as tunneling and control dielectric. The Al-rich AlN contains excess Al NCs which exhibits a memory effect is utilized for charge storage layer. The crystalline properties, film composition, morphology, thickness of AlN were analyzed from XRD, Auger, SEM. The grain size of Al NCs embedded in AlN films were measured by high resolution TEM. The High frequency capacitance versus voltage (C–V) measurement was utilized to determine the dielectric constant of AlN film and to exhibit the window of flat-band voltage shift of AlN/Al-rich AlN/AlN/n-Si capacitor by using HP 4294.The AlN and Al-rich film deposition were carried out by RTA-MOCVD system on n-type, (100)-oriented Si wafer. Precursor TMAl which is carried by Ar mixed with NH3 at temperature of 600-900oC and operating pressure of 0.1-10 torr was performed for deposition. Various flow rate ratio of Ar and NH3 were used for adjusting the size of Al NCs embedded in AlN film. For AlN films, XRD spectrum shows AlN and Al2O3 peak. Auger depth profiling has been conducted on the samples, and it is found that there are Al, N, and O element with 47%, 32%, and 19% existing in the films, respectively. From SEM inspection, the thickness of AlN was 15 nm. The dielectric constant of deposited AlN was measured of 6.13. The high resolution TEM shows that the excess Al form NCs in Al-rich AlN film. The Al NCs grain size with large flow rate ratio of Ar and NH3 is about 9-18 nm. The grain size of Al NCs can be scaling down to 5-10 nm by decreasing the Ar flow. A 300 nm Al layer was then deposited on the top of the AlN/Al-rich AlN/AlN/n-Si layered structure to form the electrode pad for capacitors. For memory measurement of Al/AlN/Al-rich AlN/AlN/n-Si capacitor, the charging and discharging effects of Al NCs shows the 2.5-6 V shift swept from 10~25 to -10~-25 V and returned to 10~25 V. The width of hysteresis curves widens as the sweep voltage range broadens. Further, a negative 2 V flat-band shift was achieved by programming at 15 V for 1 ms, indicating positive charge trapping in the Al NCs. Further, the retention and endurance of AlN/Al-rich AlN/AlN/n-Si capacitor will be reported for memory characterization.
6:00 PM - G6.12
Quantitative Study of Trapped Charges in Nano-Scale Ge Islands probed by EFM Measurement.
Zhen Lin 1 , Pavel Brunkov 2 , Fraud Bassani 3 , Georges Bremond 1
1 Institute of Nanotechnology in Lyon, National Institute of Applied Sciences in Lyon , Lyon France, 2 , Ioffe Physico-Technical Institute RAS, Saint-Pétersbourg Russian Federation, 3 , IMINP, Lyon France
Show AbstractInjection and detection of localized charges in nanostructures, on or below the surface, are the key issues in the field of nanoelectronics. Electrostatic force microscopy (EFM) is proved to be one of the most efficient tools not only for atomic scale characterisation of surfaces1-3 but also for local surface modification and structuring in sub-micrometre and nanometre ranges4-6. Using a conductive tip, it is possible to electrically bias the oscillating tip with respect to the sample and characterize materials for accurate local and non-destructive electrical properties for a wide range of characterisations such as surface potential, charge distribution7-8, doping concentration9 and dielectric constant10. This ability has been used to study the distribution of trapped charges in various types of samples such as individual quantum dots11-13. Such confined samples were few studied by EFM at room temperature. However, such nanostructures have a great interest because the injected charge carriers are constrained in their propagation, and interact in a finite geometry. In this work, individual Ge nanostructures on top of a 5 nm thick silicon dioxide layer thermally grown on an n+ type doped silicon (001) substrate has been charged by a conductive EFM tip and characterized at room temperature. From the EFM phase signal images, clear electron cloud could be seen. After being injected into the Ge island, these charges diffuse around in all directions homogeneously for hours which could be observed from the area of electron cloud. The nanostructures become iso-potential and behave like a conductor. Furthermore, we use a truncated capacitor model to approximate the capacitance between the tip and the sample surface. The analytical expression of the quantity of trapped charges in the Ge nanodot as a function of the EFM phase signal was deduced. Applying a tip bias of -7V during 3 minutes leads to the injection of about 750 electrons in an individual Ge island.
6:00 PM - G6.2
Composition, Structural and Electrical Properties of Silicon Nitride Oxide Very Thin Films (<10 nm) with Embedded Si-nanocrystals for Non-volatile Memory Applications.
Simon Perret-Tran-Van 1 2 , Caroline Bonafos 1 , Bernard Despax 2 , Kremena Makasheva 2 , Pierre-Eugene Coulon 1
1 , CEMES CNRS Université de Toulouse, Toulouse France, 2 , LAPLACE CNRS Université de Toulouse, Toulouse France
Show AbstractMemory devices consisting of metal-oxide-semiconductor field-effect transistor (MOSFET) with nanocrystals (NCs) are promising candidates for high-storage density low-power memory applications. The aim of our work is to demonstrate the efficiency of Si-NCs embedded in SiOxNy very thin film (<10 nm) deposited by Pulsed Plasma Enhanced Chemical Vapor Deposition (PPECVD) on silicon to produce non-volatile memory devices. Structural study performed in High Resolution Transmission Electron Microscopy (HRTEM), Energy Filtered TEM coupled to Electron Energy Loss Spectroscopy in scanning mode by using a nanometer probe (STEM-EELS) show the presence of amorphous nanoparticles already in the as-deposited layers. These particles then crystallize after annealing at high temperature (1100°C) under N2. The N content in the matrix, measured by STEM-EELS is around 7% in the as-deposited sample and do not evolve after annealing. This value is in agreement with the one deduced from Ellipsometry measurements. Post annealing under N2+O2 have been performed allowing on one hand to monitor the nanocrystal size, density and volume fraction by separating the connected nanoparticles. On the other hand this process permits to create a tunnel oxide separating the nanocrystals from the channel of the device through the oxidation of the Si substrate. The influence of the tunnel-oxide thickness and the nanocrystal population characteristics on the electrical properties has been studied by performing C(V) measurements.
6:00 PM - G6.3
Nanocrystal Memory Device Utilizing GaN Quantum Dots by RF MBE.
Panagiotis Dimitrakis 1 , E. Iliopoulos 2 3 , P. Normand 1
1 Inst. of Microelectronics, NCSR Demokritos, Aghia Paraskevi Greece, 2 Physics Department, University of Crete, Heraklion Greece, 3 Microelectronics Group, IESL-FORTH, Heraklion Greece
Show AbstractDuring the last decades, a significant number of alternative technologies have been proposed to overcome the scaling issues of conventional floating-gate Flash memories. The concept of replacing the continuous polysilicon floating gate by a 2-D distribution of discrete nanocrystals (NCs)or quantum dots (QDs) has been proposed. Huge research effort was given last decade on the manufacturability and viability of this concept. Nanocrystal nonvolatile memories (NCNVM) have been realized by the majority of the memory manufacturers evaluating a number of semiconducting and metallic NC. These investigations affirmed the enhanced scaling properties of the NC-NVMs downto 90nm but revealed issues in terms of NC uniformity (e.g., in size, in density, in spatial concentration) and retention/operation speed dilemma. In order, to answer the retention/operating speed dilemma work-unction engineering is required regarding the NC material. Metallic NCs offer higher flexibility compared with conventional Si or Ge NCs. Nevertheless, their manufacturability seems to be limited due to contamination restrictions. In this direction semiconductor NCs with negative conduction band offset (NCBO) compared to Si seems as the ultimate approach. We propose the use of GaN QDs by RF-plasma assisted MBE which can be grown on thin injection dielectrics. More specifically, GaN QDs 7nm to 20nm in diameter were grown by Stranski-Krastanov mechanism on 3.5nm SiO2 and 7nm Si3N4 injection dielectrics on p-type Si substrates. The effect of growth temperature and nitridation process on the size and the density of QDs were investigated by AFM and SEM measurements. Following, the QD layer was covered by sputtered SiO2 capping dielectric and finally standard MIS capacitor diodes were fabricated by depositing and patterning Al gate electrodes. Electrical characterization in terms of C-V and I-V measurements has shown significantly large memory windows (>3V) at low applied gate voltages (3-4V). Pulsed program and erase operation have been used in order to characterize the speed performance of the fabricated memory structures. Finally, charge retention measurements at high temperatures (150C) were performed revealing the attractive characteristics.
6:00 PM - G6.4
Formation of Ge Nanocrystals in High-k Dielectric Layers for Memory Applications.
Panagiotis Dimitrakis 1 , V. Ioannou-Sougleridis 1 , P. Normand 1 , C. Bonafos 2 , S. Schamm 2 , A. Mouti 2 , B. Schmidt 3 , J. Becker 4
1 Inst. of Microelectronics, NCSR Demokritos, Aghia Paraskevi Greece, 2 , CEMES-CNRS, Universite de Toulouse, Toulouse France, 3 , Research Center Dresden-Rossendorf, Dresden Germany, 4 , Cambridge Nanotech Inc, Cambridge, Massachusetts, United States
Show AbstractSemiconductor nanocrystals (NCs) have been employed successfully in various demonstrators for new CMOS device applications like nonvolatile memory (NVM) cells [1] and optoelectronic components [2]. Ge nanocrystals are of special interest for nano-floating gate NVM cells due to their negative conduction band offset with respect to the Si substrate conduction band; an attractive NC property for faster programming speeds and longer retention times compared to silicon NCs. Another interesting option is the use of high-k materials as tunneling dielectrics. This route has been examined to overcome the charge retention issues rising from the thinning of the injection SiO2 layer. Based on the above, Ge-NCs embedded in high-k dielectrics provide a promising alternative in the development of NC-memories.ALD Al2O3 and HfO2 layers, 5nm and 7nm thick, grown on Si substrates and subjected to 1keV Ge+ implantation at doses of 0.5 and 1E16cm-2 were fabricated. Next, the implanted layers were covered with an additional 10nm-thick layer. Post-implantation furnace annealing (PIA) studies in N2 ambient were carried out in order to investigate the effect of annealing temperature on the formation of Ge-NCs by Transmission Electron Microscopy (TEM) and spectroscopic ellipsometry. Electrical and memory characteristics were studied utilizing Al-gate MIS capacitor structures fabricated by conventional photolithography and Al etching techniques. Control samples, i.e., with non-implanted Al2O3 and HfO2 but annealed following the same thermal budget like the implanted layers, were also fabricated.TEM and Electron Energy Loss Spectroscopy (EELS) studies revealed the presence of Ge-NCs only in Al2O3 layers, with 5 nm mean diameter at a tunneling distance of 1 to 3 nm from the Si substrate. Further analysis revealed the presence of an interfacial layer (SiO2-rich) of 1 nm thick between the Al2O3 layer and the Si substrate as well as crystallization of the alumina matrix. Capacitance-to-voltage (C-V) measurements performed at various test ac-signal frequency exhibit hysteresis due to charge storage in implantation-induced-defects and NCs. The reduction of the C-V hysteresis, in terms of ΔVFB, at 1050C might be related with the Ge out-diffusion and disolution of very small Ge-nanoclusters. Current-to-voltage (I-V) characteristics after PIA reveal the dominant injection mechanism. I-V characteristics clearly suggest that both crystalline phases strongly affect the carrier injection and current conduction through the Al2O3 layer especially at low electric fields.
6:00 PM - G6.5
Formation and Evolution of Ge Nanocrystals by Low-energy Ion Implantation in SiN/HfO2 Stack Layers for Non-volatile Memory Applications.
Marzia Carrada 1 , Bhabani Sahu 1 , Abdelillah Slaoui 1 , Caroline Bonafos 2 , Pierre-Eugene Coulon 2 , Jesse Groenen 2 , Sandrine Lhostis 3
1 InESS, InESS-UDS-CNRS, Strasbourg, Strasbourg, France, 2 Groupe Nanomat , CEMES-CNRS – Université de Toulouse, Toulouse France, 3 , ST Microelectronics, Crolles France
Show AbstractThe use of nanocrystals embedded in a SiO2 matrix as charge storage elements in novel non-volatile memory devices has been widely explored in the last decade. Recently, the replacement of the SiO2 by a dielectric with higher permittivity (high-k) has been proposed in order to improve data retention and programming speed of non volatile memory devices. Indeed, the use of nanocrystals in high-k dielectrics seems to be a promising option for deep-submicron floating-gate memory technology, even if their fabrication is not straightforward. In this work, we have investigated the formation of Germanium nanocrystals (Ge-ncs) in SiN/HfO2 stack layers by low energy ion implantation and subsequent thermal annealing. When Ge+ was implanted into metal organic chemical vapor deposited (MOCVD) thin HfO2 layers (thickness ≤ 9 nm), a non-uniform distribution of the implanted Ge atoms on the wafer had been observed due to electrostatic charge accumulation. With subsequent thermal annealing, a significant amount of Ge out-diffused from the film and the rest of the Ge piled up at HfO2/Si interface. The processing issues regarding low energy ion implantation of Ge+ have been discussed in detail, and the problem has been solved by depositing a thin SiN cap layer with electron cyclotron resonance-chemical vapor deposition (ECR-CVD) on HfO2 films prior to ion implantation, which, in turn, can act as a barrier layer to suppress the diffusion of Ge atoms. Ge+ has been implanted at 5 keV with different doses ranging from 1 × 1016 to 2 × 1016 cm-2 (i) within a 3 nm thick SiN layer deposited on top of a 9 nm thick HfO2 layer, and (ii) within a 12 nm thick SiN layer deposited on top of a 5 nm thick HfO2 layer and further annealed at 800 °C for 30 min under N2. The formation and evolution of Ge-ncs have been investigated using Rutherford back scattering spectroscopy (RBS), Raman spectroscopy, HRTEM, EFTEM, and STEM-EELS techniques. We have succeeded in the formation of an array of well separated spherical Ge-ncs close to the HfO2/SiN interface. Furthermore, metal-insulator-semiconductor (MIS) capacitors were fabricated consisting of a thin (5 – 9 nm) HfO2 tunnel dielectric, Ge-ncs as charge storage elements, and SiN as control dielectric. Large memory windows (> 4 V) with negligible contribution from interface states has been achieved at relatively low sweeping voltage (≤ 6 V), indicating the utility of these trilayer structures for low operating voltage non-volatile memory devices
6:00 PM - G6.6
CVD Growth and Passivation of W and TiN Nanocrystals for Non-volatile Memory Applications.
Guillaume Gay 1 , Djamel Belhachemi 1 , Jean-Philippe Colonna 1 , Stephane Minoret 1 , Arnaud Beaurain 2 , Bernard Pelissier 2 , Marie-Christine Roure 1 , Eric Jalaguier 1 , Gabriel Molas 1 , Thierry Baron 2 , Barbara De Salvo 1
1 , CEA LETI MINATEC, Grenoble France, 2 , LTM-CNRS, Grenoble France
Show AbstractIn this paper, we present growth and passivation of tungsten (W) and titanium nitride (TiN) nanocrystals (NCs) on silicon dioxide and silicon nitride for use as charge trapping layer in floating gate memory devices. W and TiN are chosen for being compatible with MOSFET memory fabrication process. NCs are deposited in an 8 inches industrial CVD Centura tool. W NCs are processed in two steps: first, a silane soak saturates the silicon oxide with SiH4 molecules which will be used as nucleation sites, and then W nucleates by reduction of WF6 by SiH4 at 440°C. Thereby, fluorine atoms are evacuated in the gas phase SiF4(g). TiN NCs are deposited using TiCl4(g) and NH3(g) at 680°C. SEM characterizations are made on these NCs. Average W NCs size is 6 nm with a 7E11 cm-2 density. In the case of TiN NCs, average NCs size of 4nm with a density larger than 1E12 cm-2 is obtained. For both TiN and W, we observe good NCs size uniformity on the 8 inches diameter wafers.X-ray photoelectron spectroscopy (XPS) measurements are made in order to know the metal chemical states in the NCs. At ambient atmosphere, both W and TiN NCs are fully oxidized, with various oxidation levels. In order to passivate NCs before exposure to oxygen, metal NCs are exposed to dichlorosilane (SiH2Cl2) in-situ at 550°C. Silicon is selectively deposited on metal NCs, which is creating a silicon shell around the metal core. Since silicon oxidation is thermodynamically favourable compared to W oxidation, silicon is an oxygen getter and W is protected from oxidation. In the case of TiN NCs, titanium is partially oxidized but a metallic core subsists after exposition to ambient. However, this passivation is not sufficient to protect NCs from oxidation during following high thermal budget MOSFET fabrication steps. In order to protect better NCs from oxidation, we have included NCs in a silicon nitride matrix which is a good diffusion barrier to oxygen. After high temperature annealing (1050°C under N2 during 1 minute) XPS measurements point out that TiN NCs encapsulated by silicon nitride are not oxidized further, which makes them good candidates for being used as charge trapping layer in floating gate memories.
6:00 PM - G6.7
Formation of Nickel Silicide Nanocrystal Double Layers for Nonvolatile Memory Applications.
Yoo-Sung Jang 1 , Jong-Hwan Yoon 1
1 Department of Physics, Kangwon National University, Chuncheon, Gangwon-do, Korea (the Republic of)
Show AbstractNonvolatile memory (NVM) devices employing nanocrystal (NC) floating gates offer many advantages over conventional structures, and there are additional advantages in using metallic nanocrystals instead of semiconducting nanocrystals. Furthermore, well-defined nanocrystal multilayers have high potential for NVM device applications with large storage capacity. In this study, we report the direct growth of crystalline nickel silicide (NiSi) nanocrystal double layers in silicon. NiSi nanocrystal double layers were formed by thermal annealing of a sandwich structure comprised of a thin Ni film sandwiched between two silicon-rich oxide (SiOx) layers. The Ni-sandwiched SiOx layers were thermally annealed samples in a quartz-tube furnace using high purity nitrogen gas (99.999%) as an ambient. This treatment might cause bidirectional Ni diffusion into SiOx to react with excess Si atoms, resulting in NiSi nanocrystals. The microscopic structure of annealed SiOx layers, and the size and crystallinity of NCs were studied by transmission electron microscopy (TEM). The chemical composition of NCs was analyzed by energy dispersive X-ray spectroscopy (EDS) using an energy dispersive spectrometer attached to the TEM instrument. The method is shown to produce well-defined crystalline NiSi NC double layers. The MOS capacitors provided with SiO1.5 and 0.3 nm Ni film, which is annealed at 900 oC for 3 hrs are shown to exhibit large memory window, multilevel charge storage, and long retention characteristics suitable for multibit memory applications.
6:00 PM - G6.9
The Chemistry of Colloidal Pt Nanoparticles Solutions for Thin Film Deposition.
Virginie Latour 1 , Andre Maisonnat 1 , Yannick Coppel 1 , Vincent Colliere 1 , Bruno Chaudret 1 , Pierre Fau 1
1 equipe L, Laboratoire de Chimie de Coordination CNRS, Toulouse France
Show AbstractMetal nanoparticles and self assembled nanostructures are now commonly spreading in many applications such as new gas sensors, electronics, catalysis, or medicine.[1,2] In particular, owing to their strong charge confinement, platinum nanoparticles have recently attracted the interest of physicists in the field of non volatile memories.[3] In consequence, the development of simple methods for the chemical synthesis of stable, surface controlled and nanosized Pt particles able at forming a dense thin film on a substrate is of major interest.[1] A method of preparation based on the decomposition of organometallic precursors in organic solvents has been developed in our team for several years.[4,5] It offers a great versatility in particles compositions, shape, size and surface chemistry. The latter parameter is of great interest in the scope of the use of colloidal solutions for an efficient surface coating.We present in this talk the formation of a very stable colloidal solution of platinum nanoparticles able at being deposited on various substrates. We have used platinum dimethyl cyclooctadiene precursor (Pt(COD)(CH3)2) and studied its low temperature decomposition in toluene medium in the presence of CO reducing gas. It results in the formation of a black precipitate containing aggregated nanosized particles of platinum. This dense superstructure is spectacularly re-dispersed in the same solvent upon a simple air exposure, and lead to a very stable and homogeneous Pt colloidal solution (Figure 1). NMR and analytical techniques (IR, TEM, XRD) were used to evidence the reactions pathways for the Pt nanoparticles redispersion and stabilization. Thanks to the control of this surface chemistry, the resulting colloidal solution can be implemented to form 2D films of Pt nanoparticles on silicon substrates by simple method such as spin or dip coating (Figure 2). This technique opens the way to a simple route for making dense and controlled layers of Pt clusters on various surfaces.[1] G. A. Somorjai, F. Tao and J. Y. Park, Top. Catal., 2008, 47, 1 [2] L. Erades, D. Grandjean, C. Nayral, K. Soulantica, B. Chaudret, P. Menini, F. Parret and A.Maisonnat, New J. Chem., 2006, 30, 1026 [3] S. R. Puniredd, C. M. Yin, Y. S. Hooi, P. S. Lee and M. P. Srinivasan, J. Colloid Interface Sci., 2009, 332, 505.[4] A. Rodriguez, C. Amiens, B. Chaudret, M.-J. Casanove, P. Lecante and J. S. Bradley, Chem. Mater., 1996, 8, 1978. {5] E. Ramirez, L. Erades, K. Philippot, P. Lecante and B. Chaudret, Adv. Funct. Mater., 2007, 17, 2219.
G7: Poster Session: Advanced Flash II
Session Chairs
Panagiotis Dimitrakis
Hang Ting Lue
Tuesday PM, April 06, 2010
Exhibition Hall (Moscone West)
6:00 PM - G7.1
Bandgap-engineered Tunnel Barriers for Silicon-rich Silicon Nitride Floating Gate Nonvolatile Memory Applications.
Eunkyeom Kim 1 , Seungman An 2 , Taekyung Yim 2 , Kyoungwan Park 1 2
1 Department of Nano engineering, University of Seoul, Seoul Korea (the Republic of), 2 Department of Nano Science & Technology, University of Seoul, Seoul Korea (the Republic of)
Show AbstractThe SONOS memory device becomes more attractive in recent years because the scaling capability is more compatible with the logic devices and it has advantages of simple fabrication processes and low voltage operation. However, there are still some problems, such as short retention and poor endurance. A silicon-rich silicon nitride (SRSN) film has been in stead investigated as a new charge trap layer to increase the trapping efficiency and enlarge the operation window. In addition, the bandgap engineered (BE) tunnel barrier was proposed in the SONOS type charge-trap memory devices to improve the nonvolatile memory characteristics. In this work, we fabricated a SRSN BE tunnel barrier floating gate memory device and investigated the nonvolatile memory behaviors. The SRSN floating gate memory devices with a BE tunnel barrier of a stacked SiNx/SiO2 or SiO2/SiNx/SiO2 were fabricated. In the BE tunnel barrier formation, the bottom SiO2 film was thermally grown on the silicon-channel substrate using a dry oxidation furnace, and SiNx film was deposited in PECVD system, where the SiNx is a nitrogen-rich silicon nitride. The second SiO2 film in the BE tunnel barrier, if any, was grown in PECVD. The SRSN thin layer as a charge storage node was successively deposited on the BE tunnel barrier using by PECVD system. The control gate SiO2 oxide was formed on the SRSN layer by LPCVD. From the threshold voltage shift measurements along the stress voltage and time duration, large memory window (>~3 V) and long retention time (>10years) were obtained. It was found that the BE tunnel barrier positively affects the SRSN floating gate memory operation. The memory characteristics of the program/erase and retention at the SRSN layer that depend on the BE layer will be discussed in detail.
6:00 PM - G7.2
Nonvolatile Memories Using Charge Traps Formed in HfO2 Films by Nb Ion Implantation.
Min Choul Kim 1 , Suk-Ho Choi 1 , K. Belay 2 , Rob G. Elliman 2
1 Department of Applied Physics, Kyung Hee University, Yongin, Kyungkido, Korea (the Republic of), 2 Electronic Materials Engineering Department, Australian National University, Canberra, Australian Capital Territory, Australia
Show AbstractWe demonstrate the feasibility of an approach to nonvolatile memory that exploits charge trapping at local-state energy levels or charge traps formed in HfO2 by Nb ion doping. For this approach, Si wafer/5 nm SiO2/25 nm HfO2 structures were implanted with Nb ions of 60 keV to nominal fluences in the range from 1012 to 1015 cm-2 and subsequently annealed in a rapid-thermal-annealing apparatus at a temperature of 600 oC for 5 min under nitrogen ambient. The implanted Nb ions are expected to form such local-state energy levels in the band gap of HfO2 based on simple calculations. The memory properties were analyzed by capacitance-voltage (C-V) measurements. The samples with fluences of 1012 to 1013 cm-2 show large counter-clockwise C-V hysteresis loops, indicating the electron injection from substrate to the charge-trapping layer containing Nb atoms. The hysteresis width or the memory window increases from 3.6 to 4.9 V at sweep voltages of ±15 V with increasing the implant fluence. In contrast, the samples with fluences of 1014 to 1015 cm-2 do not show any C-V hysteresis loops. Photocurrent spectra were also measured to characterize the charge-trap levels and compared with the theoretical calculations. Memory properties including program/erase speeds, endurance, and retention time are also presented.
6:00 PM - G7.3
Charge Trapping Memories With Atomic Layer Deposited High-k Dielectrics Capping Layers.
Nikolaos Nikolaou 1 , Panagiotis Dimitrakis 1 , Pascal Normand 1 , Konstantinos Giannakopoulos 2 , Vassilios Ioannou-Sougleridis 1 , Kaupo Kukli 3 4 , Jaakko Niinisto 3 , Mikko Ritala 3 , Markku Leskela 3
1 Institute of Microelectronics, NCSR "Demokritos", Aghia Paraskevi, Attika Greece, 2 Institute of Materials Science, NCSR "Demokritos", Aghia Paraskevi, Attika Greece, 3 Department of Chemistry, University of Helsinki, Helsinki Finland, 4 Institute of Physics, University of Tartu, Tartu Estonia
Show AbstractThe continuation of scaling of the standard floating gate non-volatile memory devices faces many difficult challenges, such as further reduction of the control and the tunnel oxides thicknesses and also due to the floating gate interference. Silicon nitride charge trapping technology offers an alternative scaling route, provided that the over-erase effect will be circumvented. This approach implies the introduction of high permittivity dielectric layers that will replace either one or more of the constituent layers of the oxide-nitride-oxide typical stack gate. The replacement of the dielectric layers is usually combined with high work function metal gates in order to suppress electron injection from the gate, during the erase operation. The Atomic Layer Deposition (ALD) constitutes a preferred deposition method for the growth of high-k dielectric layers. A critical aspect of this technology is the choice of precursors and the chemical reactions, factors which determine the quality and the properties of the deposited layer. In this work we examine the influence of ALD precursors to the memory properties of oxide-nitride-metallic oxide non-volatile gate memory stacks. Typical oxide-nitride stacks (2.4 nm / 5 nm) were grown on n-type Si substrates. ALD ZrO2 or HfO2 layer were deposited on top to a thickness of 10 nm approximately. Both metal oxides were deposited using either alkylamides [Zr[N(C2H5)(CH3)]4] or cyclopentadienyls [(CpMe)2Zr(OMe)Me], and ozone as oxygen source. Standard Pt capacitors were fabricated. For the case of the ZrO2 gate stacks a memory window of 6 V was determined, comprised of 4V write window and 2 V erase window. The I-V, C-V and charging characteristics showed no significant differences between the ZrO2 layers synthesized by the two different precursors. In terms of reliability the alkylamide precursors provides ZrO2 layers with higher dielectric strength. In case of HfO2 blocking layers the memory window and the dielectric strength are significantly affected by the precursor. More precisely, alkylamide formed HfO2 shows a write window of 7 V while the cyclopentadienyl formed HfO2 shows 5 V. Pulsed operation reveals that HfO2 based gate stacks exhibit reasonable charge trapping after the application of voltage pulses 11 V at 0.1 ms.
6:00 PM - G7.4
Low Temperature Growth of Silicon Structures for Application in Flash Memory Devices.
Thomas Mih 1 , S Paul 1 , Richard Cross 1
1 Emerging Technologies Research Centre, De Montfort University, Leicester United Kingdom
Show AbstractThe continuous down-scaling of flash memory cell layers is approaching a dead end where leakage currents will increase significantly and impact data retention. This challenge, coupled with the requirements of dielectric quality [1] may result in less integration and performance gains leading to flash performance and reliability being seriously degraded. Three-dimensional (3-D) cell architecture is one solution suggested to avert these problems and boost the performance of flash devices [2, 3]. It is attractive as it permits the integration of long-retention and high-density cells without compromising device reliability [4]. However, high temperature processing of memory layers is not ideal for 3-D stacked memory architecture, as it stresses device structures- especially at interfaces between different materials. We have developed a novel methodology, which involves an initial substrate preparatory ritual, of growing high-quality silicon structures at ≤ 400 degree Celcius [5]. This method by-passes the long hours of annealing necessary for the solid-phase crystallisation of amorphous silicon. We have previously demonstrated the suitability of this growth technique for future 3-D flash memory technology [6]. In this study, we have used metal-insulator-semiconductor (MIS) devices, which mimic memory devices, to demonstrate the suitability of the low temperature grown silicon structures for application in flash memory devices. Capacitance-Voltage studies were undertaken to understand the charging and retention time. An in-depth study of the structural, optical and electrical properties of thin-film silicon structures grown by this novel technique will also be presented. References[1] Greg Atwood, IEEE Transactions on Device Materials Reliability (2004), 4, 3001, [2] D. Park, K. Kim, B.I. Ryu; “3-D nano-CMOS transistors to overcome scaling limits” in Proc. Solid-state and Integr. Circuits Technol. (2004), 1, 34-35[3] S. Koliopoulou, P. Dimitrakis, D. Goustouridis, P. Normand, C. Pearson, M.C. Petty, H. Radamson and D. Tsoukalas, Microelectronic Engineering, 83, (2006), 1563[4] R. Tsuchiya, M. Izawa, S. Kimura, “Prospects of Si semiconductor devices and manufacturing technologies in nanometer era”, Hitachi Review (2006), 55(2), 46-55[5] S.Paul (This work will be communicated to nature; shortly).[6] T.A. Mih, R.B. Cross, S. Paul, “A novel method for the growth of low temperature polycrystalline silicon for 3-D flash memory” in Materials and Technologies for 3-D Integration, edited by F. Roozeboom, C. Bower, P. Garrou, M. Koyanagi, P. Ramm (Mater. Res. Soc. Symp. Proc. Volume 1112, Warrendale, PA, 2009) 1112, E05-03
G8: Poster Session: MRAM II
Session Chairs
Manuel Bibes
Yoshihisa Fujisaki
Tuesday PM, April 06, 2010
Exhibition Hall (Moscone West)
6:00 PM - G8.1
Spin Dynamics in Ferromagnetic Nickel Films: Influence of Surface Scattering.
Mircea Vomir 1 , Amani Zagdoud 1 , Jean-Yves Bigot 1
1 Institut de Physique et Chimie des Matériaux de Strasbourg, CNRS, University of Strasbourg, Strasbourg France
Show AbstractFor many applications in spintronics, it is important to preserve the polarization of the spins during their transport or their injection into nano-circuits. In that context, it is particularly important to understand the role of surface assisted spins scattering which may decrease the efficiency of the spins transport. In the present work, we propose an approach towards the understanding of spins scattering in ferromagnetic nanostructures. For that purpose, we have studied the spins dynamics in ferromagnetic nickel films of different thicknesses. Instead of an electronic injection, the spins are excited above the Fermi level with femtosecond laser pulses having different photon energies (1.55 eV and 0.25 eV respectively). The spins dynamics is then observed during their thermalization to the Fermi level by performing time resolved magneto-optical experiments with near infra-red probe pulses. Our results show that the spins thermalize faster in the thinner nickel films, demonstrating that the spin scattering is more efficient. This effect also depends on the density of spins initially excited with the femtosecond laser pulses. The Ni samples are polycrystalline films made by Molecular Beam Epitaxy on glass substrates, with respective thicknesses of 7, 15 and 40 nm. The femtosecond probe pulses are issued from an amplified Titanium Sapphire oscillator (798 nm; 5 kHz; 48 fs). The pump pulses are either degenerate with the probe pulses or at a wavelength of 5 μm, obtained by difference frequency generation from an optical parametric amplifier. The density of absorbed photons in the Ni films varies from 0.08 to 4 mJcm-2. The magneto-optical Kerr and Faraday rotation and ellipticities of the linearly polarized incident probe pulses are measured as a function of time, density of excitation and wavelength of the pump pulses. We will present a detailed analysis of the influence of these parameters on the spin dynamics.
6:00 PM - G8.2
Low Temperature Deposition of Ferromagnetic Ni-Mn-Ga Thin Films From Two Different Targets via rf Magnetron Sputtering.
A. Lourenco 1 , F. Figueiras 1 , S. Das 1 , M. Peres 2 , N. Soares 1 , M. Pereira 1 , N. Santos 2 , N. Sobolev 2 , V. Amaral 1 , Andrei Kholkin 3
1 Dept. of Physics, CICECO, University of Aveiro, Aveiro Portugal, 2 Dept. of Physics, I3N, University of Aveiro, Aveiro Portugal, 3 Dept. of Ceramics and Glass Engineering, CICECO, University of Aveiro, Aveiro Portugal
Show AbstractFerromagnetic shape memory alloy films have great potential for multiferroic applications due to a multitude of useful properties and possible integration with ferroelectrics. In this work, Ni-Mn-Ga thin films were prepared by rf sputtering co-deposition of two targets of Ni50Mn50 and Ni50Ga50 on (0001) sapphire and (100) Si substrates at 400 °C. SEM cross-section of the films reveals a thickness of approximately 120 nm and a columnar type structural growth. Energy dispersive X-ray spectroscopy confers an atomic composition of the films of Ni56Mn19Ga25. Conventional XRD analysis at room temperature shows for both films the co-existence of a significant amorphous structure with some degree of crystallinity. However, we could clearly identify both cubic and tetragonal phases on sapphire whereas film on Si shows mainly the tetragonal phase.Magnetic measurements (in-plane M-H hysteresis loops) using vibrating sample magnetometry revealed strongly ferromagnetic behavior with well-defined hysteresis loops of similar shape both at room (300 K) and at low temperatures (150 K). The films exhibited narrow hysteresis loops, low coercivity (~100 Oe) and high saturation magnetization of ~200 emu/cc. Ferromagnetic resonance (FMR) measured in the X-band (~9.47 GHz) in the temperature range from 280 K to 400 K evidenced a Curie temperature of about 350 K for both films. No in-plane anisotropy in FMR spectra was detected. The absence of in-plane anisotropy and the similarity in magnetic behavior indicates that the magnetic properties of as-deposited films are independent of substrate and are completely governed by the co-deposition procedure and growth conditions.This study also reveals that co-sputtering of the complementary targets enables to control the Mn/Ga composition by the ratio of magnetron power during the co-deposition. The process is effective in achieving the thermodynamic conditions to deposit thin films of the Ni-Mn-Ga austenitic phase (highly magnetic at room temperature) at relatively low substrate temperature without need for post-deposition annealing or further thermal treatment, which is a relevant requirement for the device fabrication.The work is partly supported by the EC-funded project “Multiceral” (NMP3-CT-2006-032616).
6:00 PM - G8.3
Magnetostatic Interactions of Two-dimensional Arrays of Magnetic Strips.
Leszek Malkinski 1 , Minghui Yu 1 , Seong-Gi Min 1 , Donald Scherer 1
1 Advanced Materials Research Institute, University of New Orleans, New Orleans, Louisiana, United States
Show AbstractA demand for constantly increasing information storage density gives rise to enhanced interactions between elements of neighboring MRAMs units. In order to investigate the significance of magnetostatic interactions a series of arrays consisting of NiFe stripes with dimensions of 100 nm x 300 nm x 1500 nm were fabricated using electron beam nanolithography and magnetron sputtering followed by the lift-off process. The separation between the stripes in different arrays was varied in the range between 100 nm and 2000 nm. Magnetic hysteresis loops of the arrays were measured using SQUID magnetometer for different orientations of the applied field with respect to the arrays. Magnetic anisotropy of the arrays was determined based on ferromagnetic resonance measurements at 9.8 GHz using EPR spectrometer. The measurements were carried out for different directions of in-plane and out-of-plane magnetic bias field. The angular dependence of the resonance field of the main resonant peak indicated presence of the uniaxial magnetic anisotropy due to elongated shape of the stripes. Comparison between angular curves of resonant fields for different arrays led to the conclusion that increasing strength of magnetostatic interactions among the stripes resulted in a suppression of the uniaxial anisotropy of the array. The stripes separated by 2000 nm behaved almost like non-interacting objects, but the effect of interactions became particularly significant for separations smaller than 600 nm. The properties of the arrays with the smallest separations of 100 nm resembled those of continuous films. Magnetostatic modes have been observed in the FMR spectra in addition to the main resonant peak. These modes are believed to result from dimensional confinement of lateral spinwaves in the magnetic stripes. No such modes were observed in the reference samples of solid Py films, with the in-plane applied magnetic field.
6:00 PM - G8.4
Direct Synthesis of L10-Phase Nanostructured CoPt Using Dense Plasma Focus Device Operating in Non-optimized Focus Mode.
Zhenying Pan 1 , Jiaji Lin 2 , Shumaila Karamat 1 , Paul Lee 1 , Stuart Springham 1 , Tuck Lee Tan 1 , Rajdeep Rawat 1
1 Natural Science and Science Education, National Institute of Education, Singapore Singapore, 2 , Solar Energy Research Institute of Singapore, Singapore Singapore
Show AbstractA direct synthesis of (001)-oriented nanostructured CoPt thin films has been successfully achieved using a 880 J pulsed plasma focus device (DPF) operating in a non-optimized focus mode with a low charging voltage of about 8 kV. In our investigation, the hydrogen was used as filling gas. A set of gas pressures in lower side of 0.15, 0.30, 0.50 and 0.65 mbar was investigated in the non-optimized focus mode. The SEM imaging results show that very uniform nanostructured CoPt were achieved in non-optimized focus mode with crystallite size less than 10 nm. Furthermore, the XRD results indicate that the (001) oriented fct structured L10-phase CoPt thin films have been achieved directly in as-deposited sample without any post annealing. The VSM analysis shows that the as-deposited samples have coercivity as high as 1000 Oe indicating thereby possible applications in high density data storage.
Symposium Organizers
Caroline Bonafos CEMES/CNRS
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Panagiotis Dimitrakis NCSR "Demokritos"
G9: ReRAM II
Session Chairs
Robert Elliman
Yoshihisa Fujisaki
Ruth Muenstermann
Claudia Wiemer
Wednesday AM, April 07, 2010
Room 2011 (Moscone West)
9:30 AM - G9.1
Impedance Spectroscopy Observation for Examining Resistive Switching Mechanism in TiO2 Thin Films.
Minhwan Lee 1 , Kyung Min Kim 1 , Jung Ho Yoon 1 , Cheol Seong Hwang 1
1 , Seoul National University, Seoul Korea (the Republic of)
Show Abstract The resistance switching in TiO2 thin films has been ascribed to the formation and rupture of conducting filaments around the anode/film interface. While only a certain part of the filaments actively contributes to the switching, the rest of the filaments are likely to be preserved during the switching process. Kim et al. recently suggested that bipolar switching in TiO2 film can be well explained by the space charge limited conduction (SCLC) mechanism. (K. M. Kim et al., Appl. Phys. Lett., 91, 012907, 2007) According to their work, the thin layer in the film directly facing the top Pt electrode acts as the trapping layer due to its high oxygen vacancy concentration, which has been induced by the previous anodic bias on the top electrode. The stoichiometric TiO2 resides between the trapping layer and conducting filaments. In this study, an ac impedance spectroscopy was employed to further understand the conduction mechanism in the resistive switching TiO2 film. Impedance spectra are obtained using top and bottom Pt electrodes through a 60nm TiO2 film. Impedance measurements on a cell in air show two RC components. When the sample is put in a high vacuum environment (10-6 torr range), however, only one RC component with much smaller resistance was found. Should one of the two semicircles in air be from interfacial electrochemical reaction, the circle must be considerably larger in vacuum due to the lack of charge transferring species, which in this case are oxygen ions (or oxygen molecules). This strongly indicates that the two semicircles in air are from charge transport through two distinct layers inside the TiO2 film, not from the interfacial reduction/oxidation processes. This bi-layer state around the electrode-film interface is well aligned with Kim et al.'s model ascertaining that switching in TiO2 film follows the space charge limited conduction (SCLC) mechanism where two layers - the one has high concentration of charge trapping oxygen vacancy and the other is trap-free, stoichiometric TiO2 layer - are assumed to exist near the film/electrode interface. In vacuum, the trapping layer, which is adjacent to the top electrode, is likely to make a direct (but local) contact with filaments as the oxygen vacancy concentration and the thickness of the layer grow in a highly oxygen deficient environment. An equivalent circuit with two parallel-RCs and a resistance in series was employed to fit the impedance measured in air. The resistance of the trapping layer kept growing as switching process was repeated while the resistance of underlying stoichiometric TiO2 layer was dependent on the set compliance current. The low activation energy of ~0.03eV under vacuum reassures that the major conducting species are electrons, which travels through the oxygen deficient layer with shallow trap.
9:45 AM - G9.2
Improved Resistance Switching Behavior of n-type TiO2/p-type NiO Stacked Structure.
Kyung Min Kim 1 , Seul Ji Song 1 , Gun Hwan Kim 1 , Joon Young Seok 1 , Cheol Seong Hwang 1
1 Department of Materials Science and Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show AbstractThe uni-polar type thermochemical resistance switching (RS), where the formation and rupture of conducting path (filament) governs the overall resistance switching, attracts a great deal of attention for the next generation non-volatile memory devices. However, an unacceptably long reset time (~ 1 - 100 μs) was required to acquire enough heat accumulation for rupturing the filament. Because the filament switching is localized at the anode or cathode interface for the n-type and p-type materials, respectively, a huge heat loss through the electrode must occur during the reset process. This resulted in the ineffective power utilization and longer switching time. Therefore, a shorter switching time and better efficiency are expected if the filament would be broken inside the oxide material. In this study, n-type TiO2 and p-type NiO which are the anode and cathode localized switching materials, respectively, were stacked, and the resistance switching properties of this stacked system were examined. For this stacked structure, RS was observed only when the TiO2 (NiO) was biased negatively (positively). This could be understood from the fact that the initial electron (hole) injection at the cathode (anode) interface is the prerequisite condition for the successive thermochemical reaction to occur. In addition, the shapes of the reset current-voltage (I-V) curves can be used to identify the location where the rupture of the filament occur because of the distinctive reset I-V curve shapes of TiO2 and NiO. It was found that the location where the filaments rupture could be limited to the region near the TiO2/NiO interface. This largely improved the heat efficiency for the reset process, and, thus, the reset time was reduced from ~ 100 μs for single layer TiO2 and NiO to ~250 ns. Details for the manipulation of the location for the filament rupture will also be described in detail.
10:00 AM - **G9.3
Microscopic Identity of the Conducting Filaments and Resistance Switching Mechanism in TiO2 Thin Film.
Kyung Min Kim 1 2 , Duk Hwang Kwon 1 , Jae Hyuck Jang 1 , Jong Myeong Jeon 1 , Min Hwan Lee 1 2 , Seul Jie Song 1 2 , Gun Hwan Kim 1 2 , Jun Yeong Seok 1 2 , Bora Lee 1 , Seungwu Han 1 , Miyoung Kim 1 , Cheol Seong Hwang 1 2
1 Department of Materials Science Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show AbstractThe resistance of TiO2 thin film can be switched reversibly by a voltage pulse, which can be exploited for applications in the next-generation non-volatile memory. However, the mechanism of resistance switching is unclear due to the lack of knowledge of the microscopic identity of the current path generated inside the oxides. This study observed conduction nano-filaments directly by high-resolution transmission electron microscopy (HRTEM) in a Pt/TiO2/Pt system. The HRTEM images identified the filaments and local electrical properties were confirmed by in-situ current-voltage measurements in HRTEM. Electrical conductivity measurement in pad structure sample at low temperatures also confirmed that the overall resistance switching was induced by the filaments. These results suggest that the vacancy ordering at the nanometer scale is important for the resistance-switching mechanism. The formation mechanism of such nano-filaments based on the macroscopic pulse-switching experiments will be also discussed. The burst into flow of capacitive charges at the moment of set switching determines the on-state resistance. Therefore, the capacitor size has a crucial influence on the on-state resistance of the resistance switching cell. The current overflow by the parasitic capacitance of the semiconductor parameter analyzer seriously interferes with the accurate estimation of the switching parameters. Pulse switching with a proper modeling of the circuit parasitic was essential for accurately estimating the switching parameters.
10:30 AM - G9.4
Peering Inside a Functioning Bipolar Resistance Switching Device.
John Paul Strachan 1 , Matthew Pickett 1 , J. Yang 1 , Douglas Ohlberg 1 , A. Kilcoyne 2 , Shaul Aloni 3 , Gilberto Medeiros-Ribeiro 1 , R. Williams 1
1 Information and Quantum Systems Lab, HP Labs, Palo Alto, California, United States, 2 Advanced Light Source, LBNL, Berkeley, California, United States, 3 The Molecular Foundry, LBNL, Berkeley, California, United States
Show AbstractA wide range of insulating materials, in particular transition-metal oxides, exhibit electrical polarization-dependent resistance changes. Although well-characterized electrically, direct observations of the physical changes induced during this switching have been limited, due to the challenges of observing subtle material changes occurring in a small volume buried between two metal contacts. Here we use synchrotron-based x-ray absorption spectromicroscopy and transmission electron microscopy (TEM) in order to determine the chemical and structural identity of the switching region in a functioning Pt/TiO2/Pt device. Devices were fabricated on substrates that were transparent to both soft x-rays and 200 keV electrons. Using these transmission techniques allows probing of the physical properties of the active switching layer between or during the application of an electrical bias. We have directly observed the formation of a conductive channel following an electroforming process and the material changes induced by the subsequent switching. The conductive channel is identified to be a nanoscale metallic suboxide (TiO2-X), a phase generated within the TiO2 matrix by the creation and ordering of oxygen vacancies. Besides shedding light on some long-standing questions about the physical changes underlying bipolar resistance switching, we also show how this work has informed new device engineering.
10:45 AM - G9.5
The impact of Oxygen Vacancy Configurations on the Conductance Channel in Rutile TiO2 for Resistance Switching Memory.
Seong-Geon Park 1 , Blanka Magyari-Kope 1 , Yoshio Nishi 1
1 , Stanford University, Stanford, California, United States
Show AbstractReRAM is very promising for advanced non-volatile memory technologies in terms of high density, better non-volatility, and fast switching speed. Up to date, a number of different switching characteristics have been established in a variety of material systems. In fact, it has been known that a number of combinations of an oxide with metal electrodes can exhibit resistance switching characteristics. Therefore, several models have been proposed so far, such as charge trapping, the formation of conductive filament, the modulation of Schottky barrier, and electrochemical reduction and oxidation. However, none of these models is completely understood, and in order to elucidate the operating principles accurately, in-depth understanding of the resistance switching mechanism at the atomistic level is necessary. In this study, we performed first-principle simulations based on density functional theory (DFT) to study the effect of oxygen vacancy defects on the electronic structure of rutile TiO2 using the local density approximation with correction of on-site Coulomb interactions (LDA+U). It is widely believed that defects play an important role in the switching between conducting and insulating states in transition metal oxides. In fact, it has been shown that oxygen vacancies in TiO2 create localized electronic states in the band gap, thus n-type conducting behavior has been discussed in oxygen deficient TiO2. We have already demonstrated that mono-vacancy gives rise to a spin polarized defect state at 0.4 eV below conduction band minimum. When it comes to on-state conduction during resistance switching, however, it is necessary to consider the interaction between multi-oxygen vacancies. First we investigated the effect of di-vacancy with several different configurations. A strong interaction between oxygen vacancies was observed especially in (110) plane di-vacancy configuration which two vacancies lie in the same (110) plane. The number of defect states within the band gap increase in the case of di-vacancy However, in case of out of (110) plane di-vacancies which two vacancies do not lie in the same (110) plane, the amount of the splitting of defect energy states is almost negligible, which suggests that there are preferential interactions between the electrons along special directions. Furthermore, we found that most of the defect states generated by di-vacancy were located near the conduction band minimum. This fact suggests that electron doping could be more probable if oxygen vacancies exist as the form of a vacancy cluster. We also investigated the filament type of structure, which is composed of a chain of oxygen vacancies, i.e. as conductance channel in ReRAM devices. In particular, vacancy filament results in more discrete defect states within the band gap leading to the defect assisted electron transport from valence band to conduction band which may account for on-state low resistance conduction in bulk rutile TiO2.
11:00 AM - G9:ReRAM-2
BREAK
11:30 AM - **G9.6
Operational Aspects of Cation-based Resistive Memory.
Michael Kozicki 1
1 Center for Applied Nanoionics, Arizona State University, Tempe, Arizona, United States
Show AbstractIt is generally accepted that the adoption of novel materials and device structures will be necessary to circumvent the limitations posed by charge-storage memory elements as we move beyond the 32 nm node of the International Technology Roadmap for Semiconductors (ITRS). This is particularly true in the case of non-volatile memory (NVM), where current technologies will struggle to meet the performance and 3-D integration requirements of next generation memory and storage. One solution to this major issue involves devices that can be switched between two or more non-volatile resistance states. Currently, several resistance-change or ReRAM (resistance-based random access memory) technologies show promise but many lack complete scalability in that they have a physical size or programming power that is excessive for ultra-high density memory or mass storage system applications. One of the most promising resistance-change variants utilizes ion-conducting films. A solid electrolyte is placed between two electrodes to form a device which may be switched from high- to low-resistance states by the formation of a nanoscale conducting pathway created by ion transport and redox reactions. The resistance is returned to the high value via the application of a reverse bias or a high-current forward bias, both of which result in the dissolution of the conducting filament, albeit by different mechanisms.This paper will focus on the operational aspects of cation-based resistive memory, and in particular on devices which have a silver- or copper-containing oxide or higher chalcogenide electrolyte sandwiched between oxidizable and inert (ohmic or rectifying) electrodes. Such devices are written by applying a forward bias (oxidizable electrode positive with respect to the inert electrode) and the on-state resistance is controlled via the programming conditions, allowing multi-level storage by the formation of several discrete resistance states. The mechanism responsible for these states appears to involve an initial fast electrolyte bridging process, followed by radial growth of the initial filament, both processes being driven by ion migration. The erase can be performed using a forward (“unipolar” programming) or reverse (“bipolar” programming) bias, although bipolar erase typically requires substantially less current as it also relies on ion migration for the dissolution of the filament rather than being dominated by Joule heating as in the unipolar case. The paper will include a discussion of the effects of write-erase cycling on device parameters and will demonstrate that a rectifying electrode may be used in compact (4F2) integrated diode-isolated passive structures.
12:00 PM - G9.7
Towards a Quantitative Description of Solid Electrolyte Conductance Switches.
Monica Morales-Masis 1 , Hans-Dieter Wiemhofer 2 , Jan M. van Ruitenbeek 1
1 Leiden Institute of Physics, Leiden University, Leiden Netherlands, 2 Institut für Anorganishe und Analytische Chemie, Universität Münster, Münster Germany
Show AbstractThe present technology of solid state memory devices, largely dominated by flash type memory, is continuously scaling down to smaller devices. Lately, the concept of electrically induced resistance switching has been proposed as one of the approaches towards the realization of nanoscale memories. These memories have a metal-insulator-metal configuration, where the insulator can be a.o. a metal oxide, a polymer or a solid electrolyte. We have investigated the electrical conductance properties and transport mechanisms for both ions and electrons within a solid electrolyte, in order to develop a fundamental understanding of the physical properties of such nanoscale memory devices. We present a quantitative analysis of the steady state ionic and electronic transport in a solid electrolyte device that leads to resistance switching.Using Ag2S as the model material for such solid electrolyte devices, we have fabricated Ag2S thin films and measured their memory resistive properties (Morales-Masis et al., Nanotechnology 20, 095710(2009)). In a series of experiments, the Ag2S thin films are contacted to different electrodes: a Ag or Pt thin film as the bottom electrode and a Pt wire or Pt-coated AFM tip as the top electrode. When a bias voltage is applied to the electrodes, it induces both ionic and electronic transport within the solid electrolyte. While the electrons are free to move between the electrolyte and the electrodes, the ions cannot cross the barrier of the Pt contact, and accumulate near that electrode. In the case of small applied voltages (before reduction of Ag+-ions occurs), this is observed as a strongly nonlinear (exponential) current-voltage (I-V) curve. We have fully modeled this electrical behavior using the Hebb-Wagner theory which describes both the electronic and ionic transport in the solid electrolyte, up until the resistance switching. This model, based on irreversible thermodynamics, includes the contact shape and size, film thickness and all physical properties of the electrolyte. Ongoing experiments with materials like e.g. Cu2S and AgGeSe are focused at generalizing the developed model to a wider range of mixed ionic-electronic conductors. In the case of higher applied voltages, when Ag2S decomposes, the redox reaction (Ag+ + e− ↔ Ag metal) takes place at one of the electrodes. The electrochemical growth and dissolution of Ag metallic filaments is then responsible for the full bipolar resistance switching. In the low resistance state, the device shows several multiples of quantum conductance. We have found this conductance to be proportional both to the applied bias voltage and to the size of the top electrode.
12:15 PM - G9.8
Ionic and Electronic Transport in Silver Chalcogenide – Germanium Chalcogenide Nanocomposites.
Robert Wang 1 , Ravisubhash Tangirala 1 , Delia Milliron 1
1 The Molecular Foundry, Lawrence Berkeley National Laboratory, Berkeley, California, United States
Show AbstractIonic conductivity enhancements of several orders of magnitude have been demonstrated in nanoscale heterostructures.[1,2] Additionally, the high-temperature superionic conducting state of silver iodide can be stabilized down to ~30°C in nanocomposites.[3] Enhancing ionic conductivity and/or stabilizing superionic conducting states is of relevance to ion-migration-redox resistive switching memory. To explore these nanosize effects we have developed a modular method for the preparation of nanocomposites. Specifically, we prepare nanocomposites consisting of silver chalcogenide nanoparticles of variable size and composition embedded in a germanium chalcogenide matrix also of variable composition. Using a combination of impedance spectroscopy and x-ray diffraction, we report the ionic conductivity, electronic conductivity, and crystal state of these nanocomposites from 25°C to 230°C.[1] Sata et al., Nature, 408, 946 (2000).[2] Garcia-Barriocanal et al., Science, 321, 676 (2008).[3] Makiura et al., Nat. Mat., 8, 476 (2009).
12:30 PM - G9.9
Structural Details and Structural Engineering of Ge-rich Chalcogenide Glasses for Nanoionic Nonvolatile Memory.
Maria Mitkova 1 2
1 Electrical and Computer Engineering, Boise State University, Boise, Idaho, United States, 2 Electrical and Computer Engineering, Boise State University, Boise, Idaho, United States
Show AbstractOne of the most fascinating applications of chalcogenide glasses is related to formation of a nanoionic conductive bridge nonvolatile memory. It is realized in the programmable metallization cell (PMC) memory devices, which utilize the oxidation and reduction of nanoscale quantities of metal ions in solid electrolyte films. The formation of a robust but reversible conducting pathway by way of electrodeposition at low voltage and current reduces the resistance of the electrolyte by several orders of magnitude. In this manner non-volatile memory is achieved in elements that are highly electrically and dimensionally scalable and fulfill the requirements of the International Technology Roadmap of Semiconductors for decade ahead. The main active materials for the solid electrolyte films for creation of the PMC devices so far are Ag doped Ge-chalcogenide glasses since they offer great structural and thermal stability and assure good device performance. The usual way of formation of thin films from them is by sputtering which results in composition containing more than 40 at. % Ge. Our recent studies show that this structure is characterized with appearance of a new Raman mode at 410 cm-1 which we describe as a stretching mode of a mixed Ge-S chains forming in these films. The model is discussed on hand of numerous data from Mössbauer spectroscopy, EXAFS study, atomic orbital theory, and ab initio simulation.Saturation of such material with high concentration of Ag for formation of solid electrolyte material is difficult to achieve due to the high depletion of chalcogen. This fact can compromise the device performance to a great extend. To overcome this, we suggest initiation of oxygen assisted photoinduced changes of the chalcogen depleted material as a method for material’s engineering. In this respect we report our results of illumination of Ge46S54 chalcogenide glass films with band gap light in air. The outcome of this process is formation of Ge-S backbone rich in chalcogen. We relate this to consumption of part of Ge available in the initial material by occurrence of a photoinduced oxidation. The former is proved by Energy Dispersion Spectroscopy which showed a presence of 17.68 at% oxygen in the glass post radiation. Raman spectra demonstrate that the initial material shows breathing modes, characteristic for Ge46S54 glass. After illumination in oxygen containing atmosphere, the Raman spectra reveal structure characteristic for composition of the Ge-S backbone close to Ge33S67 in which as shown by our previous studies one can introduce over 30 at. % Ag. The oxide forms a film on the surface and this changes the surface relief, studied by atom force microscopy, as well as by following the Raman activity during the photo-oxidation process.
G10: ReRAM III
Session Chairs
Jianhua Joshua
Michael Kozicki
Wednesday PM, April 07, 2010
Room 2011 (Moscone West)
2:30 PM - **G10.1
Resistive RAM: Prospects and Challenges for Scaled Memory Applications.
Dirk Wouters 1
1 , IMEC, Leuven Belgium
Show AbstractResistive switching RAM (ReRAM) has gained a lot of recent interest as potential candidate technology for scaled (non-volatile) memory applications. An important class of ReRAM is based on filamentary switching in metal-oxides (typical binary transition metal-oxides), where operation is linked to diffusion of oxygen vacancies eventually combined with thermal driven oxidation/reduction processes (giving rise to bipolar resp. unipolar operation). For successful application in scaled memory application, however, a number of important challenges need to be resolved, namely integration compatibility (e.g. using CMOS friendly electrode materials), good switching statistics and reliability, and scaling of program currents and of the switching process itself. Given the importance of the electrode material, understanding the material physics of the combined BE/MOx/TE stack is thereby a crucial aspect.The paper will show the progress that has been made on these issues for a number of important metal-oxide material systems.
3:00 PM - G10.2
Nanoscale RRAM With Intrinsic Diode Characteristics.
Kuk-Hwan Kim 1 , Sung Hyun Jo 1 , Siddharth Gaba 1 , Wei Lu 1
1 Electrical engineering and Computer Science, Univ. of Michigan, Ann Arbor, Ann Arbor, Michigan, United States
Show AbstractCrossbar structures based on two-terminal resistive switches have been investigated for a number of applications such as high-density memory (RRAM), programmable logic, and adaptive neuromorphic circuits due to the high density and large connectivity offered by the simple two-terminal devices. For practical applications of the crossbar structure, crosstalk due to sneak path originated from reversely biased cells has to be suppressed. The 1D1R approach using an extrinsic diode to suppress the reverse current is however not compatible with bipolar RRAM devices which require a negative voltage for the off-on transition. Here we report studies on nanoscale resistive memory devices that exhibit intrinsic diode-like I-V characteristics at on-state. The reverse bias current in these devices was suppressed to below 10-13 A with a rectifying ratio > 106 without the application of extrinsic diode components. The intrinsic diode-like characteristics are robust during device operation and can survive > 108 write/erase programming cycles. The devices are based on the motion of Ag ions in nanoscale a-Si pillars. They can be programmed at 2 V programming voltages without the initial high-voltage forming process. Muitibit storage capability was also reported. We believe the intrinsic diode characteristics provide a possible solution to suppress crosstalk in high-density crossbar memory or logic arrays particularly for those based on bipolar resistive switches (memristors).
3:30 PM - G10.4
Planting Nanoscale Seeds of Switching Centers by Diffusion in Memristive Switches.
J. Joshua Yang 1 , John Paul Strachan 1 , Douglas A. Ohlberg 1 , Philip Kuekes 1 , Ronald Kelley 1 , William Stickle 1 , Duncan Stewart 1 , G. Medeiros-Ribeiro 1 , R. Stanley Williams 1
1 , Hewlett-Packard Laboratories, Palo Alto, California, United States
Show AbstractFirst prominent about 40 years ago (1), electrical resistance switching in conductor/insulator/conductor structures has regained significant attention in the last decade (2, 3), motivated by the search for alternatives to conventional semiconductor electronics. Recent results have shown promising device behaviors for a variety of applications (4). In order to use these devices into a real circuit, it is crucial to be able to control such device properties as switching polarity, device yield and device variance (5). We demonstrate these key control abilities by controllably seeding the oxide-based crosspoint switches with nanoscale (0.5-1 nm) switching centers that are induced by the thermal diffusion of a reactive material through the bottom electrodes of the devices. This simple procedure has yielded a dramatic improvement in device yield to over 98% and enables establishment of a favored switching polarity. Physical characterization of devices with and without these seeds confirm and explain the crucial role they play. These results lead to both a better understanding of the physics of memristive switches and also open an avenue to engineer device properties. (1) G. Dearnaley et al., Electrical phenomena in amorphous oxide films. Rep. Prog. Phys. 33, 1129 (1970). (2) R. Waser et al., Nanoionics-based resistive switching memories. Nature Mater. 6, 833 (2007). (3) J. Joshua Yang et al., Memristive switching mechanism for metal/oxide/metal nanodevices. Nature Nanotechnol. 3, 429 (2008). (4) J. Joshua Yang et al., A Family of Electronically Reconfigurable Nanodevices. Adv. Mater. 21, 3754 (2009). (5) J. Joshua Yang et al., The mechanism of electroforming of metal oxide memristive switches. Nanotechnology 20, 215209 (2009).
3:45 PM - G10.5
Multiple Structural Changes of Local Nanogap Sites for Resistance Switching Effect Using Gold Nanogap Junction.
Hiroshi Suga 1 , Masayo Horikawa 1 , Shunsuke Odaka 2 , Hisao Miyazaki 2 , Kazuhito Tsukagoshi 2 , Tetsuo Shimizu 1 , Ysushisa Naitoh 1
1 Nanotechnology Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan, 2 Research Center for Materials Nanoarchitectonics (MANA), National Institute for Materials Science (NIMS), Tsukuba, Ibaraki, Japan
Show Abstract Nanogap junctions, nanometer-spaced electrodes, have been used to investigate the electrical properties of nanosized materials, such as molecules and nanoparticles. Recently, it was found that a bare nanogap junction exhibits a reversible resistance switching effect that is dependent on the intensity of the applied voltage between the nanogap junction. [1] Such nanogap junctions have potential for application in future nonvolatile memory devices. [2] The nanogap resistance switching (NGS) effect occurs as a result of atom migration on the electrode surface, the migration of which induces structural changes in the gap width (tunneling distance) when the applied voltage is greater than a critical voltage, which is dependent on the electrode material.[3] The current-voltage (I-V) characteristics of the nanogap junction exhibit negative differential resistance (NDR) due to structural changes of the gap width. However, details of the structural changes of local sites have not been observed, due to the lack of resolution of our FE-SEM, so that it is difficult to determine how many local sites contribute to the tunneling path. In this study, the dependence of the tunneling emission area, i.e., the total area of tunneling paths across a nanogap, on the resistance switching effect was investigated to clarify the contribution of local sites for NGS effect. Gold nanogap junctions with different line widths of 45, 90, 640, and 1280 nm were fabricated using electron beam lithography and a controlled electromigration method for nanogap formation, [4] and the dependence of the NGS effect on the line widths was investigated. For all line widths, the measured I-V curves exhibit a transition from a high resistance state to a low resistance state and the voltages at maximum current are not dependent on the line width. However, the maximum current increase with NDR are decrease from 800 to 80 µA as the line widths decrease. To confirm that the decrease in the peak current is caused by the variation of the tunneling emission area, the tunneling emission area was estimated from the current-voltage characteristics using the tunneling equation. [5] Parameters which were obtained from the results of the fitting curve indicate that the differences in the tunneling current are mainly caused by the emission area. It is concluded that NGS effects occur as a result of multiple structural changes at local sites on the electrode surface. Reference: 1) Y Naitoh et al. : Nanotechnology 17 (2006) 5669. 2) Y. Li et al. : Nat. Mater. 7 (2008) 966. 3) S. Furuta et al. : Jap. J. Appl. Phys. 47 (2008) 1806. 4) D. R. Strachanan et al.: Appl. Phys. Lett. 86 (2005) 043109. 5) G. Simmons: J. Appl. Phys. 34 (1963) 1793.
4:00 PM - G10: ReRAM-3
BREAK
G11: FeRAM I
Session Chairs
Manuel Bibes
Eisuke Tokumitsu
Wednesday PM, April 07, 2010
Room 2011 (Moscone West)
4:30 PM - **G11.1
Overview and Technical Trend of Chain FeRAM.
Daisaburo Takashima 1
1 Center for Semiconductor Research & Development, Toshiba Corp., Yokohama Japan
Show AbstractA chain FeRAMTM is the best solution to realize high-density, high-speed and low power nonvolatile memory. In this paper, the overview of chain FeRAM, the key techniques and the technical trend for FeRAM scaling and the marketing strategy for chain FeRAM are presented. First of all, the concept and basic operation of chain FeRAM are described. Second, the status of chain FeRAM and the developing trend and the key circuit and device techniques installed in 16Kb, 8Mb, 32Mb, 64Mb and 128Mb chain FeRAMs are presented. One key technique is bitline capacitance scaling in proportional to cell capacitor shrink without chip area penalty. A Quad-/Octal-Bitline architecture enables sufficient cell signal, thank to small bitline capacitance. The other is the introduction of new memory cell structure. The stacked and nested chain cell fits to memory cell shrink. The rest is the cell capacitor shrink without capacitor damage. High-density hydrogen barrier cover film over PZT material suppresses degradation of cell polarization even in 0.1um2 capacitor of 128Mb. Third, the reliability issues are discussed. The MOCVD-PZT with SRO electrode shows excellent fatigue and data retention properties. Fourth, the future direction of chain FeRAM is discussed. The vertical capacitor is one of candidates for gigabit scale chain FeRAMs, and solves signal problem and achieves small 4F2 cell without contact formation. Finally, the marketing strategy to take full advantage of chain FeRAM is presented. A nonvolatile FeRAM cache is the promising candidate to achieve high bandwidth memory system. The application of chain FeRAM to Solid-State Drive (SSD) and Hard-Disk Drive (HDD) and its system performance improvement are demonstrated. 1.5 times higher performance for SSD and 1.12~3.3 times higher performance for HDD have been obtained.
5:00 PM - G11.2
Inlaid Al2O3 Tunnel Switch Layer for Improving the Ferroelectric Performance of the Ultra-thin Pb(Zr,Ti)O3 Thin Films.
An Quan Jiang 1 , Hyun Ju Lee 2 3 , Gun Hwan Kim 2 3 , Min Hyuk Park 2 3 , Cheol Seong Hwang 2 3
1 Department of Microelectronics, Fudan University, Shanghai China, 2 Department of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 3 Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show AbstractThe realization of sufficient ferroelectricity in ultra-thin poly-crystalline films, e.g. Pb(Zr,Ti)O3 with thicknesses < 50 nm, has been hindered by various adverse interfacial interferences. In this study, a few nanometer-thick Al2O3 tunnel switch layer was introduced to the poly-crystalline Pt/Pb(Zr,Ti)O3/Ir ferroelectric capacitor with the thickness range of Pb(Zr,Ti)O3 from 50nm to 500nm. Although the presence of such a non-ferroelectric layer has previously been believed to be detrimental to the functionality of the ferroelectric capacitor, it surprisingly improved the ferroelectric performance and reliability. The unique interplay between the ferroelectric PZT and interposed Al2O3 layers results in unexpected dramatic improvement in the ferroelectric performance of ultra-thin poly-crystalline (not ideal at all) PZT films. Apart from the previous interpretation on the detrimental influence of a non-ferroelectric layer on the ferroelectric performance, the new functionality of the thin dielectric layer as an almost ideal tunnel switch was observed. It opens up during FE switching with a threshold field of Eth=12±1 MV/cm, minimizing the adverse interference with FE switching, but closes rapidly during the non-switching or post-switching over voltage stress. The latter effect largely improved the retention properties of the non-ideal FE capacitor. The thinner PZT film (50 nm) showed better FE performance than the thicker film (150 nm) once the all the adverse effects had been blocked by the interposed Al2O3 layer.
5:15 PM - G11.3
Interface Control of MOCVD-PZT Deposition Process for Highly Reliable 128Mb Chain FeRAMTM.
Takayuki Okada 1 , Hiroshi Nakaki 2 , Soichi Yamazaki 2 , Katsuaki Natori 1 , Koji Yamakawa 1 , Iwao Kunishima 1 , Takeshi Hamamoto 1 , Akihiro Nitayama 1
1 Device Process Development Center, Corporate R& D Center, Toshiba Corporation, Yokohama Japan, 2 Advanced Memory Development Center, Toshiba Corporation Semiconductor Company, Yokkaichi Japan
Show AbstractFerroelectric Random Access Memory (FeRAM) is one of the most promising candidates of a universal memory which requires non-volatile, low-power consumption, high-speed and high-density characteristics. 128Mb Chain FeRAMTM is the highest density FeRAM to date that is the first step toward realizing the universal memory [1-3]. One of the most critical factors for a high reliability of FeRAM capacitors is to precisely control deposition processes of a ferroelectric PbZrTiO3 (PZT) film to exert the best performance of the material. In this paper, we focused on the interface properties between a bottom electrode and the PZT film which dominate a good electrical property of integrated capacitors as small as 0.19 um2. PZT thin films were deposited on a Ir/TiAlN bottom electrode by MOCVD method. To understand the impact of the interface properties on the PZT capacitor performance, Pb, Zr and Ti compositions at the interface were systematically examined. The impact of deposition temperatures was also examined. Electrical properties were characterized by using IrO2/SRO/PZT/Ir/TiAlN integrated capacitors fabricated based on Chain FeRAMTM integration processes. Our results indicated that the PZT films with higher interface Pb concentration showed a larger polarization independent of the PZT crystallinity. On the other hand, although the Zr/Ti ratio at the interface affected the crystallinity of the PZT, its impact to the electrical properties was limited. Detailed TEM analysis revealed an important role of a interface Pb distribution on the ferroelectric properties. By a careful control of the interface conditions based on these understandings, a large signal voltage of the integrated capacitors for high density FeRAMs was realized. In the presentation, a physical model of the robust interface formation mechanism will also be presented.[1] I.Kunishima et al., SSDM 2009, Extended Abstract, pp.1194-1195[2] Y.Shimojo et al., VLSI Technology 2009, Tech. Dig. pp. 218-219[3] H.Shiga et al., ISSCC 2009, Tech. Dig. 27.5.
5:30 PM - G11.4
Polarization Reversal in the Pt/Pb(Zr,Ti)O3/Pt and Pt/Al2O3/Pb(Zr,Ti)O3/Pt Ferroelectric Capacitors.
HyunJu Lee 1 2 , Gun Hwan Kim 1 2 , Min Hyuk Park 1 2 , Cheol Seong Hwang 1 2
1 Department of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show AbstractPolarization reversal in ferroelectric thin films proceeds through a nucleation of domain with reversed polarization and its growth mechanism. Recently, Jiang et al. (Phys. Rev. B 80, 024119 (2009)) reported that Landauer’s paradox, where the activation energy barrier for the nucleation calculated theoretically is much higher than the experimentally determined value, can be resolved by considering the charge injection from electrode into domain wall of a reversed nuclei. In addition, they estimated the critical dimension for reversed domain nuclei (~ 4.5 nm). However, the effect of the polarization reversal direction on the nucleation of reverse domain is still not examined. In this study, polarization reversal in dielectric Al2O3/ferroelectric Pb(Zr,Ti)O3 (PZT) stacked thin film capacitors with various Al2O3 thicknesses was examined using the pulse switching measurement technique for the different direction of polarization reversal. The variation of switching current with time showed a large difference according to the direction of polarization reversal. The contact resistance associated with the property of the interface between electrode and ferroelectric (or dielectric) layer varied with the applied voltage. In addition, when Al2O3 layer was thick enough to act as a stable tunnel switch layer, the change of the contact resistance as a function of the applied voltage was more significant during the polarization reversal from downward to upward direction than the opposite case. This suggests that the domain reversal is dependent on the type of interface where the nucleation of reversed domain occurs. It is believed that, in our Al2O3/PZT stacked capacitor, the nucleation for the reversal from upward to downward polarization is dominant at bottom-Pt/PZT interface, whereas the nucleation for the reversal from downward to upward polarization is dominant at Pt/Al2O3 interface.If an arbitrary resistor is connected externally to the pulse switching measurement circuit, the applied voltage dependence of the contact resistance can be decreased. This may help examining which interface is preferable for the nucleation of reverse domain, and whether electron or hole injection is responsible for the charge compensation at the domain wall of reversed nuclei. In addition, a charge injection mechanism for the formation of stable reversed nuclei can be examined in this way. Additional results using load resistors will be reported in the presentation.
G12: Poster Session: ReRAM IV
Session Chairs
Yoshihisa Fujisaki
Judit Lisoni
Thursday AM, April 08, 2010
Salon Level (Marriott)
9:00 PM - G12.10
Microstructural Modifications in Pt/TiO2/Pt Nano-Structures During and After Electroforming and Resistance Switching.
Herbert Schroeder 1 , Ramanathaswamy Pandian 1
1 IFF, Forschungszentrum Juelich GmbH, Juelich Germany
Show AbstractUnipolar or bipolar resistance switching in metal/insulator/metal (MIM) thin film stacks have been extensively investigated for the last few decades due to their potential for future non-volatile memory devices (NVM: ReRAM). Among the various choices, TiO2 is one of the promising candidates for this purpose with several advantages including a large resistance contrast between the high and low resistance states and low power consumption. Despite the clear observation of the resistance hysteresis and promising technical qualities for the device applications, the factors originating the resistance switching under the electric field (voltage or current) remain elusive. The microscopic nature of resistance switching and charge transport in such devices is still under debate. However, the resistance hysteretic behavior is expected to have connections with some sort of atomic rearrangements that modulates the electronic current. Since transmission electron microscopy (TEM) is one of the powerful tools able to unravel the interconnections between changes of the microstructure and resistance switching, we performed both in-situ and ex-situ TEM studies on the electroforming and resistance switching process. For this purpose we produced MIM capacitor-like structures with sputtered (30nm) TiO2 films sandwiched between (20-60 nm thick) platinum electrodes with different geometries including the so-called nano-cross-bars which are essential for the future ultra-large scale-integrated memory chips because of its simplicity. From the TEM bright-field images and selected area electron diffractions patterns (SAED) the observed microstructural variations upon the electroforming and resistance switching processes will be reported. The SAED patterns indicate that there are variations in the degree of crystallinity (i.e. orientation changes and appearance of new nano-crystalline phases) upon the forming and consecutive switching cycles. Since the effect of the electron beam on the specimen is kept minimum, these microstructural changes are attributed to the forming and switching processes.
9:00 PM - G12.11
High Temperature Operation of High Impedance TiOx Memristive Devices.
Feng Miao 1 , Joshua Yang 1 , Julien Borghetti 1 , Matthew Pickett 1 , Gilberto Medeiros-Ribeiro 1 , R. Stanley Williams 1
1 , Hewlett-Packard Laboratories, Palo Alto, California, United States
Show AbstractTo tap into the promising prospects of TiOx based memristive devices for non-volatile and ultra-high density memory applications, low current and high temperature (85°C) operation are required. The precise nature of the mechanisms for switching will basically determine the switching rate and retention characteristics of such devices, which are the ultimate parameters one needs to engineer. Here we report on temperature dependent transport experiments on 50nm × 50nm cross bar devices. Resistances at room temperature in the OFF state reached values of 0.5TOhm with the switching current of sub-5 μA and an OFF/ON ratio of about 100 in steady state. Temperature cycles from RT up to 85°C were reproducible for both ON/OFF states to within a factor of 2, which allows for a significantly wide ON-OFF gap. Temperature dependent switching rates were characterized as a function of temperature and voltage, for both ON and OFF switching, reaching 100ns at about 5V for room temperature operation. The resistances in the ON and OFF state exhibited a semiconducting behavior, decreasing with temperature, with activation energy of about 200meV. Upon setting the device to an ON state, the device resistance exhibits a transient phenomenon, which starts at an OFF/ON ratio of about 1000 relaxing to an OFF/ON ratio of about 100. This transient is quite peculiar, including stochastic jumps on the resistance, which accommodate after about 500s. These transients were not particularly deterministic revealing the discrete nature of the switching process. For the given temperature range and operating voltages, we did not observe a clearly defined thermally activated mechanism. By studying the temperature dependence, we compare the low current switching behavior with virgin state smooth switching and high current stable switching behaviors, which have been observed on the same devices. The different switching mechanisms coexisting in such devices will be discussed, in the context of low current memristors for low power, non-volatile memory applications.
9:00 PM - G12.12
Electrical Properties of Ta2O5 Thin Films for ReRAM Prepared by Reactive RF Magnetron Sputtering Method.
Natsuki Fukuda 1 , Hidenao Kurihara 1 , Kazumasa Horita 1 , Yoshiaki Yoshida 1 , Yutaka Kokaze 1 , Yutaka Nishioka 1 , Koukou Suu 1
1 Institude of Semiconductor and Electronics Technologies, ULVAC,Inc., Susono, Shizuoka, Japan
Show AbstractRecently the Flash Memory is scaling limit, Thus the Memory of various types is now under study for the next generation large capacity nonvolatile memory. Resistance random access memory (ReRAM) is attracts much attention due to its advantage for integration in the next generation nonvolatile memory, because it is depend on scaling by lithography compared with the Flash Memory of capacity type. The material for ReRAM is classified roughly into binary oxides and perovskite oxides. Several binary oxides such as a Ta2O5 have the advantage for low-temperature process and low-cost materials compared with perovskite oxides such as a (Pr,Ca)MnO3. In this study, Ta2O5 film with the thickness of 10nm were prepared by reactive RF magnetron sputtering on 8inch-Pt/Si substrate using a Ta metal target in oxygen ambient. The sputtering system was the multi chamber type mass production tool. The Ta2O5 thin film was amorphous phase as a result of measurement by X-ray diffraction meter. Ta top electrodes with 50 μm diameters were deposited on the surface of Ta2O5 layer by the DC sputtering method using a shadow mask. The “Forming” voltage of TaOx-ReRAM was 3.0V. After “Forming” process, the “Set” and “Reset” voltage were 2.2V and –3.0V respectively. It has good switching properties with large on/off resistance ratio above 1,000.
9:00 PM - G12.13
Switching Mechanism of Cu-Ta2O5-based Nonvolatile Resistive Memory.
Tohru Tsuruoka 1 , Kazuya Terabe 1 , Tsuyoshi Hasegawa 1 , Masakazu Aono 1
1 , National Institute for Materials Science, Tsukuba Japan
Show AbstractResistive switches composed of a solid electrolyte sandwiched between an electrochemical active electrode (usually Ag or Cu) and an inert metal electrode like Pt have a good potential for use as nonvolatile switches and memories in large-scale integrated circuits. This switching has observed mainly for mixed ionic and electronic conductors such as Ag2S and Cu2S. Recently, another switch, in which tantalum oxide (Ta2O5) is used as the solid electrolyte, was demonstrated in order to increase the threshold voltages above the operating voltages of complementary metal-oxide-semiconductor devices. However, the switching mechanism was not fully understood, because Ta2O5 is not generally regarded as ionic conductors. Here, we performed electrical, thermal, and electrochemical measurements for Cu/Ta2O5/Pt and Pt/Ta2O5/Pt structures to investigate the switching mechanism in more detail. We fabricated cross-point structured devices with a Ta2O5 thickness of 15 nm. Current-voltage measurements showed that nonvolatile bipolar resistive switching is observed for the Cu/Ta2O5/Pt devices, but no switching occurs for the Pt/Ta2O5/Pt devices. From current-time measurements under constant positive bias to the Cu electrode, we concluded that Cu cations transport into Ta2O5 and a Cu metal filament is formed by inhomogeneous nucleation of Cu precipitates on Pt, leading to the ON state of the device. Heat stability measurements of the ON states indicated that the device is turned OFF by increasing the ambient temperature up to 600 K, which is significantly lower than the melting point of Cu. Thus we concluded that the turn-OFF is achieved by dissolution of the Cu filament thermally assisted by relatively large current under negative bias.
9:00 PM - G12.15
Highly Uniformity of Resistive Switching Characteristics in Cr/ZnO/Pt Device.
Wen-Yuan Chang 1 , Wei-Ting Wang 1 , Cheng-Hao Hou 1 , Frederick Chen 2 , Ming-Jinn Tsai 2 , Tai-Bor Wu 1
1 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, Hsinchu Taiwan
Show AbstractResistance random access memory (RRAM) has recently attracted great attention due to its potential for replacement of flash memory in next-generation nonvolatile memory applications. However, the memory device would get stressed from switching cycling, and become unstable causing the change of device property with large fluctuation. How to effectively improve the stability of switching behavior is an essential issue for practical application of the RRAM. In this work, we fabricated and investigated the effect of electrode materials on the resistive switching characteristics in ZnO films. The ZnO-base RRAM shows a bipolar resistive switching behavior that the positive bias induces a low resistance state and the negative bias resets a high resistance state. It is interesting that the Cr/ZnO/Pt shows better uniformity of resistive switching voltages and resistance states than Pt/ZnO/Pt and Al/ZnO/Pt devices. The Cr/ZnO/Pt has more stable switching property than others because partialy oxidized interface between Cr and ZnO may act as oxygen reservoir which could provide sufficient oxygen ions to neutralize the oxygen vacancies during reset process. Nevertheless, the difference in free energy of oxide formation between Al2O3 and ZnO is too high so that the reset process is unstable in Al/ZnO/Pt device. The detail result will display in the present work.
9:00 PM - G12.16
Characteristics of ZnO Thin Film for the Resistive Random Access Memory.
Jung Won Seo 2 , Seung Jae Baik 2 , Sang Jung Kang 2 , Ji Hwan Yang 2 , Yun Ho Hong 2 , Keong Su Lim 2
2 , KAIST, Daejeon Korea (the Republic of)
Show AbstractCurrently resistive random access memory (RRAM) is an emerging class of device for next-generation nonvolatile memory device due to its simple structure, good scalability and compatibility with complementary metal oxide semiconductor technology. The resistive switching behavior has been widely observed in ferromagnetic oxide materials (Pr1−xCaxMnO3), doped perovskite oxide materials (SrZrO3), and organic materials (poly-N-vinylcarbazole), as well as in simple binary transition metal oxide materials, such as TiO2, NiO, CuO, HfO2, and ZnO. We previously reported for the first time that the room temperature fabrication of highly transparent and flexible resistive random access memory (TFRRAM) devices based on a ZnO on polyethersulfone (PES) flexible plastic substrate [Appl. Phys. Lett. 95, 133508 (2009)]. In this work, we fabricated ZnO thin film with various oxygen contents [P(%) = p(O2)/p(Ar+O2), 0% ~ 50%] and investigated the resistive switching characteristics of RRAM with different top electrodes (TE= Al, Cr, Au, Pt). For the fundamental analyses of the ZnO thin film, we performed conductive atomic force microscopy (CAFM), x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS), auger electron spectroscopy (AES), and Rutherford backscattering spectrometry (RBS). We also investigated the resistive switching mechanism using temperature-dependent transport behavior and AC impedance measurements. These results suggest that the ZnO thin film is one of the promising materials for the future nonvolatile memory devices.
9:00 PM - G12.17
High-temperature Process Endurance of Oxide/Electrode Stacking Structure for Resistance Random Access Memory.
Hisashi Shima 1 , Takashi Nakano 2 , Hiroyuki Akinaga 1
1 Nanodevice Innovation Research Center (NIRC), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Japan, 2 Advanced Technology Research Laboratories, Sharp Corporation, Fukuyama Japan
Show AbstractResistance random access memory (RRAM) having a bottom electrode (BE)/oxide/top electrode (TE) stacking structure attracts significant attention because of the potential to be the CMOS (complimentary metal-oxide semiconductor) compatible, ultrahigh density and ultrahigh speed non-volatile memory. In the previous reports on the electrode material dependence of the switching characteristics, the chemical reactions between the oxide and electrode layers yielding an interfacial layer were focused on and the correlation between the switching property and the interfacial layer was discussed. Since the interface in RRAM is a solid-solid junction, the oxidation and reduction reactions are accelerated when the junction is exposed to the elevated temperature. In view of the practical application, the switching properties should have a sufficient thermal stability because the conventional CMOS process requires RRAM to be subjected to high temperature. Here we show the improvement and the degradation of the thermal stability of RRAM depending on the electrode material. The CoO layer with the thickness of 10 nm was deposited on Pt BE by magnetron sputtering. TEs were fabricated by the lift-off process followed by the deposition of the Pt capping layer. The obtained layer structures are Pt/CoO/W/Pt and Pt/CoO/Ti/Pt. The post-deposition annealing (PDA) at 400 °C in the purified Ar ambient was carried out after TE was fabricated. When the thickness of Ti was 50 nm, resistance of all the tested devices in the virgin state of Pt/CoO/Ti/Pt decreased significantly and no switching characteristics remained after PDA. According to the electron energy loss spectroscopy (EELS), the decrease of oxygen in CoO and the diffusion of Ti to the BE/oxide interface were markedly observed. Therefore, it is considered that the oxygen gettering by Ti causes this degradation. By reducing the thickness of Ti to 5 nm, the reproducible resistance switching was observed after PDA in Pt/CoO/Ti/Pt. These results indicate that the relative volume of the electrode material to the oxide layer in addition to the combination of those elements influences the high-temperature process endurance. In Pt/CoO/W/Pt with the W thickness of 50 nm, almost no degradation of the resistance in the virgin state was confirmed, even though W is more affinitive to oxygen than Co. We attribute the excellent high-temperature process endurance observed in Pt/CoO/W/Pt to the large oxygen solid solubility in W. We considered that oxygen was supplied from W to CoO when Pt/CoO/W/Pt was exposed to the elevated temperature and the excess reduction of CoO can be prevented. Thus, it is suggested that the solid solution oxygen in the electrode material as well as the chemically reacted oxygen at the electrode/oxide interface is a key factor in order to improve the high-temperature process endurance of RRAM.
9:00 PM - G12.18
Dielectric Breakdown and Kinetic Monte Carlo Simulation of Metal Filament Retention RESET Processes for Resistive Switches.
Feng Pan 1 , Vivek Subramanian 1
1 , University of California at Berkeley, Berkeley, California, United States
Show AbstractIn recent years, various types of resistive switch memories have been developed for a range of applications in microelectronic systems. Resistive switch memories are attractive due to their current-based programming and reading schemes, low-voltage operation, potentially high retention and endurance, and good read speed. Various types of resistive switch memories have been described over the years. While varying degrees of understanding of the switching mechanisms in these memories have been provided, there is a still a substantial gap in understanding and simulation of various issues related to resistive switch memory operation. In particular, mechanistic understanding and simulation of the Retention of the process by which such switches go from a low-resistance to a high-resistance state is generally lacking. Here, we perform simulations to provide an understanding of the same. First, Kinetic Monte Carlo (KMC) simulation is performed to study the Resistive Random Access Memory (RRAM) retention issue. The KMC simulation allows us to assign different activation energies obtained from either first principle calculations or experimental results to individual particles according to their local structures and it also allow us to keep track the locations of all the particles at every time step. In this study, various effects on the device retention time such as temperature, the size of the filament and concentration of defects are analyzed and the failure distributions are presented. Second, the filament formation process is obtained for resistive switches based on a thermal breakdown mechanism. The relationship between simulation physical parameters and the morphology of the filament are shown. These results will be useful in developing a comprehensive model and simulation methodology for resistive switch memory devices.
9:00 PM - G12.3
Analysis on Resistance Change Mechanism of NiO-ReRAM Using Visualization Technique of Data Storage Area With Secondary Electron Image.
Kentaro Kinoshita 1 2 , Tatsuya Makino 1 , Takatoshi Yoda 1 , Hayato Tanaka 1 , Satoru Kishida 1 2
1 Department of Information and Electronics, Tottori University, Tottori Japan, 2 Tottori University Electronic Display Research Center (TEDREC), Tottori University, Tottori Japan
Show Abstract Various successes in raising the performance of Resistive Random Access Memory (ReRAM) such as lowering the switching current [1] and improvement of the switching speed [2] were attained. In spite of those successes, the resistance switching mechanism has not been elucidated yet. This is mainly attributed to the difficulty in applying conventional analytical methods to the resistance switching region due to the facts that resistance switching occurs in the filamentary region covered with a top electrode (TEL) and, furthermore, the thickness of the filament is very thin. Recently, it was demonstrated that both the HRS and the LRS can be written over an arbitrary area by applying the bias voltage directly to NiO films using conducting atomic force microscope (C-AFM) [3]. This technique might be breakthrough for mechanism elucidation, providing a “thick filament” without TEL. In this paper, we clarified that both the HRS and the LRS of the NiO film written by using C-AFM can be distinguished using secondary electron image (SEI) as a contrast variation. A NiO film with the thickness of 60 nm was deposited on the Pt substrate by using RF reactive sputtering method in the atmosphere of the mixture gas of Ar and O2 (Ar/O2 = 0.45/0.05 Pa). During the deposition, the RF power and substrate temperature were retained at 1 kW and 380 °C, respectively. The Rh-coated Si tip of the C-AFM, which acts as a mobile top electrode, was grounded, and a voltage was applied to the bottom electrode (BEL). First, the LRS and the HRS were written in separate 20 x 20 um2 areas by scanning the AFM-tip under dc bias voltages of +9 V and -9 V, respectively. The AFM writing had almost no effect on the topographical image, whereas the HRS and LRS can be clearly observed in the current image. Then, we observed these writing areas by using scanning electron microscope (SEM). Both the HRS and the LRS can be distinguished in SEI as a definite dark contrast, whereas both of them could not be identified in the topographical image given by the primary electron emission. Energy-dispersive X-ray spectroscopy (EDS) mapping measurement showed that there is no difference in the distribution of both carbon and Rh atoms between the inside and the outside of the writing area. This result denies the possibility that the observed dark contrast in SEI is caused by removal of airborne carbonaceous contamination layer due to Joule heating during C-AFM measurement or by Rh sticking to the surface of the NiO from the AFM-tip. Therefore the present work suggests that the C-AFM writing changes the work function of NiO. Moreover, the fact that resistance state can be identified enables us to apply conventional analytical method without complicated formation of the sample to narrow down the writing area. [1] K. Kinoshita et al., Appl. Phys. Lett. 93, 033506(2008). [2] K. Tsunoda et al., Tech. Digest IEDM 2007, p.767. [3] C. Yoshida et al., APL93, 042106 (2008).
9:00 PM - G12.4
Oxygen Vacancy Migration Barrier in NiO for Unipolar Resistive Switching.
Hyung Dong Lee 1 , Blanka Magyari-Kope 1 , Yoshio Nishi 1
1 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractTransition metal oxides (TMO) such as NiO and TiO2 have been attracting tremendous interest among engineers and scientists as one of the candidates for the next-generation resistive change memories to replace the flash memory. Bulk NiO had been studies within condensed matter physics and materials science to investigate magnetic property. With the increasing importance of point defects within TMO, new interest in simulating point defects in NiO is emerging.NiO shows relatively better reset current level for unipolar filamentary type of resistance change random access memory (ReRAM). This feature, essential for memory devices, will provide advanced application opportunities, due to the low power consumption requirements.The metallic on-state has been observed in NiO, however, the conduction and switching mechanism in this material still remains unclear. Here, we propose a physical model that incorporates the energetics of oxygen vacancy formation and the migration of the vacancies to connect in a chain-like structure.The oxygen migration barriers of stable oxygen vacancy states are obtained using density functional theory. We find that the vacancies migrate in preferred directions and the formation of the metallic filament becomes energetically favorable along these directions. The thermodynamic implications for the rupture of the filament are discussed.
9:00 PM - G12.5
Modeling of Transient Switching Characteristics of Resistance Change Oxide Devices.
Mohammad Noman 1 , Wenkan Jiang 2 , James Bain 1 , Paul Salvador 2 , Marek Skowronski 2
1 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, 2 Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Show AbstractIn the last few years, there have been significant interest in oxide based reconfigurable resistance change devices. We have carried out a theoretical study of the transient behavior of resistance switching oxide devices based on SrTiO3 (STO). In particular, we focused our time-domain simulations on the motion of oxygen vacancies and how that affects the resistance state of devices. It is well known that oxides such as STO can accommodate a large number of oxygen vacancies. Not only can these vacancies serve as electron donors in such oxides, but they are also mobile under applied electric fields. The mobility of oxygen vacancies is non-linearly dependent on the magnitude of the local field (both applied and internal fields from contact effects). We will demonstrate that an electric field on the order of 1e6 V/cm can increase the mobility of the vacancies by 6-7 orders of magnitude. By taking advantage of this non-linear effect, the distribution of vacancies can be shifted radically in time scales as short as a few nanoseconds.We performed transient simulations on metal/STO/metal heterostructures, where the oxide forms a Schottky and ohmic contact with the “top” and “bottom” metal electrodes, respectively. Although the height of the Schottky barrier is fixed by the metal work function and the electron affinity of the oxide, the width of the barrier can be significantly modified by the distribution of the mobile oxygen vacancies. By changing the vacancy concentration at the Schottky interface, a modulation in the thickness of the energy barrier is observed. It is well known that electron tunneling through a Schottky barrier is highly dependent on the barrier height and its thickness; as a result of this barrier thickness modulation, the current through the device can be modulated by 3-4 orders of magnitude owing to the varying levels of tunneling. The resulting simulated I-V curve shows hysteresis consistent with literature reports; importantly, this model uses only well-accepted physical descriptions of the drift and diffusion of electrons, holes, and vacancies under applied electric fields.A systematic analysis was also carried out concerning the role of activation energy for oxygen vacancy motion on the switching and retention time of various resistance states. Since the mobility of the vacancies is exponentially dependent on the activation energy, slight changes in activation energy can have large impact on the retention time. However, because of the non-linear nature of mobility, switching time of these devices can be kept small even when the activation energy for vacancy motion is large. This is a very desired characteristic for such devices, as this promises short switching times while ensuring long retention times. Simulation results on these topics and comparison with existing literature will be presented in detail.
9:00 PM - G12.6
Preparation of (Pr,Ca)MnO3 Thin Film by Pulse-DC Magnetron Sputtering Method for ReRAM.
Yutaka Nishioka 1 , Natsuki Fukuda 1 , Hidenao Kurihara 1 , Kazumasa Horita 1 , Yoshiaki Yoshida 1 , Yutaka Kokaze 1 , Koukou Suu 1
1 Institute of Semiconductor and Electronics Technologies, ULVAC, Inc., Shizuoka Japan
Show AbstractRecently, the Flash Memory is scaling limit for large leakage current and decreasing cell to cell coupling ratio under the 60nm node. Resistance random access memory (ReRAM) is candidate of future nonvolatile memories because of its scalability, high speed, and low power. (Pr,Ca)MnO3 (PCMO) is first report of the material for ReRAM device array using a CMOS process, its have the advantage for low power operation compared with binary oxide such as NiOx. But the properties of PCMO on Recently, the Flash Memory is scaling limit for large leakage current and decreasing cell to cell coupling ratio under the 60nm node. Resistance random access memory (ReRAM) is candidate of future nonvolatile memories because of its scalability, high speed, and low power. (Pr,Ca)MnO3 (PCMO) is first report of the material for ReRAM device array using a CMOS process, its have the advantage for low power operation compared with binary oxide such as NiOx. But the properties of PCMO on Si substrate were not understood well because many reports of PCMO were deposited on perovskite single crystal substrate such as SrTiO3, (La,Sr)MnO3 and LaAlO3. In this study, PCMO were prepared pulse-DC magnetron sputtering on 8inch Si substrate using a single ceramic target. The sputtering system is the multi chamber type mass production tool. The deposition rate was high-speed with 45nm/min. The PCMO is crystallized at 425degreeC and have (112)/(002) prefer orientation measured by X-ray diffraction meter. The PCMO thin film showed the switching characteristic, and the ratio of the current value was 1000 times.
9:00 PM - G12.7
Low Power Bipolar Resistive Switching Memory Using Cu Metallic Filament in High-k SrTiO3 Solid-Electrolyte.
Liao Kuo-Chih 1 , Shakh Ziuar Rahaman 2 , Maikap Siddheswar 2
1 Opto-electronic Engineering, Chang Gung University, Taoyuan Taiwan, 2 Electronic Engineering, Chang Gung University, taoyuan Taiwan
Show AbstractHigh-k SrTiO3 ternary oxides is very promising candidate for next generation resistive memory applications reported by several researchers. Most of the researchers have used the Pt or Au metals to get the resistive switching properties by using undoped/Cr-doped or Ni doped-SrTiO3 materials. But Pt and Au offer various problems in CMOS technology. To avoid this problem, Cu is one of the best choices for using metallic filament in the SrTiO3 solid-electrolyte. Furthermore, Cu can be commonly used in the interconnection of CMOS technology. In this study, we have investigated, for the first time, the resistive switching memory devices in a Cu/SrTiO3/W structure with the small via size of 0.2 um. Good resistive switching characteristics are obtained by using Cu metal gate electrode due to the electrochemical formation and removal of metallic pathways in the SrTiO3 film. When sweeping voltage is larger than the threshold voltage (Vth=+1.2V) then the resistive switching is observed and the maximum current is limited by current compliance of 100 uA. Beyond the negative voltage of Ve=-0.4V, the low resistance state is going to be the high resistance state. We can read the high resistance (Rhigh=4.1x10^11) and low resistance (Rlow=5.1x10^3) states at a read voltage of Vread=+0.1V. The resistance ratio of (Rhigh/Rlow) is >10^7, which is very high for multi-level data storage (MLC) applications. Good endurance of >10^2 cycles and good retention of >1 hrs are observed. A possible resistive switching mechanism is related to the electro-deposition process will lead the formation of metallic filament. This is believed that this memory device can be useful for future nano-scale non-volatile memory device applications.
9:00 PM - G12.8
Effect of Capacitive Charge on the Set-state Resistance in TiO2 Unipolar Resistance Switching Memory.
Seul Ji Song 1 , Kyung Min Kim 1 , Gun Hwan Kim 1 , Jun Yeong Seok 1 , Ranju Jung 2 , Cheol Seong Hwang 1
1 Department of Materials Science and Engineering and Inter-university Semiconductor Research Center, Seoul national university, Seoul Korea (the Republic of), 2 Department of Electrophysics, Kwangwoon University, Seoul Korea (the Republic of)
Show AbstractThe unipolar resistance switching (URS) process proceeds by applying the same bias polarity, and has been understood from the formation and rupture of the percolated conduction channels, called conducting filaments (CF), in several oxides like TiO2. CF growth was initiated by carrier injection from the cathode interface, and thermal-energy assisted field-driven migration of oxygen vacancies in TiO2. It has been reported that the set-state resistance (Rset) is almost regardless of electrode size, because electrical conduction is dominated by a local path in the oxide layer. It was also reported that URS materials usually have the non-uniform switching parameters, such as switching voltages, as well as the accompanying resistances, even though the OFF/ON ratio was sufficiently large. Therefore, it is essential to examine the controlling parameter that governs the formation and rupture of CF for the better performance of RS materials.In this study, the parameters that control the Rset of a Pt/TiO2/Pt resistive memory cell in URS mode were examined by monitoring the current flow at the moment of set switching in either voltage sweep or pulse switching modes. In I-V sweep mode, we monitored the transient current with different compliance current. When the peak current is detected, the semiconductor parameter analyzer cuts off the voltage supply after a certain transient time. This transient time must be RC delay (~ tens of μs) determined by circuit parasitic elements. The parasitic capacitance is calculated about to be 150nF. The total charge migration after reaching the peak current can be calculated by integrating the current with respect to time. Although the compliance current had some influence on the Rset, the charge stored in parasitic circuit element modified the CF in a relatively uncontrolled manner. This affects the state of the CF significantly, and Rset is not well controlled.Pulse switching with a constant current supply was performed under the high resistance state (HRS). In this system, effect of capacitive charge stored in the memory cell was confirmed without compliance response issue. For the pulse switching case, the transient current pulse has two steps corresponding to the dc leakage currents for the HRS and low resistance state (LRS), respectively. The noise components can be modeled reasonably based on the specification of the PG and ringing effect of the circuit. The difference between the measured curve and simulated curve corresponds to the capacitive charge/discharge current components. These capacitive components were fitted to a Gaussian function considering the RLC circuit model. The physical modeling results show that the stored charge bursts into flow through this CF during the switching time (~ 50 ns), and determines the resultant Rset. This suggests that the amount of the capacitive charge is the key parameter that controls the Rset, which was confirmed by the pulse switching with the different capacitor area.
9:00 PM - G12.9
Influence of Electrode Material on the Interconnect Line Resistance and Performance of Resistive Cross Bar Array Using TiO2 Thin Film.
Gun Hwan Kim 1 2 , Jun yeong Seok 1 2 , Kyung Min Kim 1 2 , Min Hwan Lee 1 2 , Cheol Seong Hwang 1 2
1 Material Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show AbstractAmong the various types of memory devices, the cross bar array is expected to offer the highest integration density with non-volatility, high operation speed and lower power consumption. However, there are a few obstacles before realization of cross bar array where stable operation is possible, such as integration of diode with proper specification and reduction of signal line resistance. In this study, various metals were examined as the electrode material in order to achieve both stable resistance switching and low enough line resistance of the cross bar array, specifically on TiO2 films. From the fabricated cross-line structure, the influence of the line resistance on the switching behavior was examined.A cross bar array and a capacitor-like MIM cell (both with Pt/TiO2/Pt stack) were fabricated for our prototype device using the common photo-lithography process. While the capacitor-like device showed stable resistance switching behavior, the cross bar array did not show the RESET process. This discrepancy between the two devices using the same TiO2 film hinted the inability to perform the RESET on the cross bar device may be due to the high signal line resistance. In this view point, a theoretical calculation on the signal line resistance required for a stable operation was performed and relevant electrical specifications were quantified.In an effort to minimize the signal line resistance, a capacitor-like cell with Al/Pt/TiO2/Pt/Al stack was tested first. The Pt layer was still used for guaranteeing the same chemical/mechanical interfaces with TiO2 film as before. The switching test on this device, however, showed Ohmic conduction, which was not suitable for resistance switching behavior. This Ohmic behavior is attributed to the fact that reactive Al metal and Pt may have made various alloys during TiO2 deposition process under oxygen plasma at high temperature. An SEM image showed morphological deformation and an XRD result showed peaks other than metallic Al and Pt signals. Even with a 10nm thick Ti layer inserted between Al and Pt to prevent the formation of alloys, it still showed unstable resistance switching although there was morphological improvement. However, using Au films instead of Al rendered a stable resistance switching on the cross bar array structure.An important impact of signal line resistance on the switching of a cross bar array was additionally found. In an 1 X 32 cross bar array, as the distance from a point on the bottom electrode to the top electrode increased, the on-state resistance also gradually increased. Even if we assume that all cells have the same operation voltage (Vset and Vreset), the voltages need to be externally supplied for the switching operation should be different.In this study, a suitable structure that enables stable resistance switching on cross bar array device was found. In addition, the specification that the signal line should satisfy for a stable switching was quantified theoretically.
Symposium Organizers
Caroline Bonafos CEMES/CNRS
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Panagiotis Dimitrakis NCSR "Demokritos"
G13: FeRAM II
Session Chairs
Cheol Seong Hwang
Daisaburo Takashima
Thursday AM, April 08, 2010
Room 2011 (Moscone West)
9:30 AM - G13.1
Dynamic Switching Behavior and Polarization Retention in Polymer Ferroelectric Films for Nonvolatile Memory Applications.
Pankaj Sharma 1 , Timothy Reece 1 , Stephen Ducharme 1 , Alexei Gruverman 1
1 Physics and Astronomy, University of Nebraska-Lincoln, Lincoln, Nebraska, United States
Show AbstractReorientation of spontaneous polarization of ferroelectric materials by an external electric field provides a physical basis for application in nonvolatile memories and mass data storage. Poly(vinylidene fluoride-trifluoroethylene), P(VDF-TrFE), is the best-known and most widely used ferroelectric polymer because of its relatively high polarization value and electromechanical activity. Recent fabrication of highly ordered arrays of P(VDF-TrFE) nanomesas for nonvolatile memory application underscored the importance of improving crystallinity to attain spatially uniform polarization distribution and nanoscale investigation of the switching behavior. In this study, resonance-enhanced Piezoresponse Force Microscopy (PFM) has been used to investigate the switching behavior of the ultrathin PVDF-TrFE films. The time-voltage dependence of the switching dynamics and polarization retention have been studied as a function of the film thickness in a wide temperature range (from room temperature up to glass transition point). PVDF-TrFE films were deposited on highly doped Si substrates using the Langmuir-Blodgett technique. Films showed significant variations of domain patterns with changes in film morphology and thickness. Generally, the relationship between the average domain size and film thickness follows the Kittel’s law. However, in individual PVDF-TrFE nanomesas with high aspect ratio significant deviation from this law has been observed. Investigation of polarization reversal within single-crystalline nanomesas has shown that the domain lateral growth is of the fractal type illustrating a strong influence of defects and interphase boundaries on domain dynamics. A two-dimensional map of the local switching parameters obtained by means of switching spectroscopy PFM was correlated with the film morphology and defect structure.
9:45 AM - G13.2
Beyond Two Orientations: Addressing Four Different Polarization States in Highly Oriented Ferroelectric Polymer Thin Films by Piezoresponse Force Microscopy.
Markus Geuss 1 3 , Martin Steinhart 2 3
1 , Adolphe Merkle Institute of the University of Fribourg, Marly Switzerland, 3 , Max-Planck-Institute of Microstructure Physics, Halle (Saale) Germany, 2 Institute of Chemistry, University of Osnabrueck, Osnabrueck Germany
Show AbstractAll-organic non-volatile data storage devices in flexible electronic systems have received broad interest. However, writing processes can only be performed with low switching voltages. This requirement is only met by ultra thin films consisting of ferroelectric polymers, such as P(VDF-ran-TrFE), with thicknesses below 100 nm. In general, the switching behavior of almost all ferroelectrics is governed by nucleation and growth of ferroelectric domains induced by external electric fields. However, it was shown that in thin ferroelectric polymer films crystallinity and consequently the attainable remanent polarization is dramatically decreased as compared to bulk systems. Only recently, oriented and highly crystalline ferroelectric polymer films with a thickness of around 30 nm were prepared on highly oriented PTFE friction transfer films (FTFs). Strikingly, these films were characterized by switching voltages of below 10 V. The unit cell of pseudo-hexagonal (orthorhombic) P(VDF-ran-TrFE) has a permanent dipole moment. Owing to the pseudo-hexagonal nature of the crystals, the dipole moment can coincide with any one of six nearly equivalent crystallographic directions so that six different polarisation states are possible. However, in switching experiments using parallel plate capacitors only "up" and "down" dipole orientations are sensed so that limited information on the actual spontaneous polarisation in the film is accessible. In contrast to inorganic ferroelectrics, domains in polymers were observed only after the application of poling pulses, e.g. by conductive AFM tips. Here, we show that only two-dimensional Piezoresponse Force Microscopy (2D-PFM) allows imaging the complex native domain structure in highly oriented, crystalline P(VDF-ran-TrFE)thin films on top of PTFE FTFs. Making use of the inhomogeneous electric field of the probe in 2D-PFM, we moreover demonstrate reversible switching of dipoles in four of the six possible orientations. Increasing the number of accessible polarization states to four significantly enhances the data storage density as compared to conventional configurations in which only two polarization states can be addressed.
10:00 AM - G13.3
In situ Studies of Ferroelectric Domain Nucleation and Wall Pinning Using Scanning Transmission Electron Microscopy and Piezoresponse Force Microscopy.
Hye Jung Chang 1 , Sergei Kalinin 2 , Nina Balke 2 , Pu Yu 3 , Ramamoorthy Ramesh 3 , Saswata Bhattacharya 4 , Long-Qing Chen 4 , Stephen Pennycook 1 , Albina Borisevich 1
1 Materials Science and Technilogy Division, Oak Ridge National laboratory, Oak Ridge, Tennessee, United States, 2 Center for Nanophase Materials Sciences, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States, 3 Department of Physics, University of California, Berkeley, California, United States, 4 Materials Science and Engineering, Penn State University, University Park, Pennsylvania, United States
Show AbstractThe mechanism of ferroelectric domain nucleation and domain-defect interactions is studied using in-situ Scanning Probe Microscope – Scanning Transmission electron microscopy studies. The 300 nm multiferroic BiFeO3 (BFO) thin film is grown on DyScO3 and has a large density of 71 degree domain walls. The electrical field is applied locally using a W tip inside the scanning transmission electron microscope (STEM). The domain formation can be detected from STEM contrast pattern likely arising from the strain associated with newly formed ferroelastic domain wall. The step-wise increase of probe bias allows detection of the critical voltage corresponding to the formation of ferroelectric domain. This critical bias for the domain nucleation can be as low as 800 mV, which is much lower than the values (2-5 V) observed by Piezoresponce Force Microscopy (PFM). The exact value of the nucleation bias is highly dependent on the sample thickness along the beam direction. At the very first stage of domain nucleation, the near-surface hemispherical domain forms, which develops as a flattened sphere in the later stage. The phase field modeling suggests the formation of through 71 degree domain (invisible due to lack of strain) and near-surface 109 degree domain, in a good agreement with experimental observations.The switching experiment in the vicinity of the preexisting domain wall has been performed. From the repeated experiments, it was found that the acute angle area with respect to the domain wall is preferential nucleation site compared to the opposite side area having obtuse angle. This agrees well with the theoretical calculation which showed asymmetric potential dip for the domain nucleation near the twin domain boundary. Finally, we observed the strong asymmetry of domain wall motion across the boundary region. Time dependence of domain diameter was measured, and revealed a logarithmic creep behavior. The future potential of STEM-SPM to study ferroelectric domain wall dynamics and other bias-induced phase transitions are discussed.The research is sponsored by the Office of Basic Energy Sciences, Division of Materials Sciences and Engineering, the Office of the Scientific User Facilities of the U.S. Department of Energy, and by appointment (H.J.C.) to the ORNL Postdoctoral Research Program administered jointly by ORNL and ORISE.
10:15 AM - G13.4
Elemental Analysis of BiFeO3 in Bulk and Thin Film Form Using X-ray Photoelectron Spectroscopy.
Ramachandran Balakrishnan 1 2 , Ambesh Dixit 3 , Ratna Naik 3 , Gavin Lawes 3 , Mamidanna Rao 1 2
1 Nano Funtional Materials Technology Centre and Materials Science Research Centre, Indian Institute of Technology Madras, Chennai, Tamil Nadu, India, 2 Physics, Indian Institute of Technology Madras, Chennai, TamilNadu, India, 3 Department of Physics and Astronomy, Wayne State University, Detroit, Michigan, United States
Show AbstractMaterials that possess several simultaneous ferroic orders are called multiferroics. The coupling between the two order parameters, called the magnetoelectric effect, is very interesting from the point of view of fundamental physics, and could also lead to applications in spintronics and other fields [1,2]. In order to use magnetoelectrics in devices, a preliminary step is to grow thin films of magnetoelectric materials. Among the possible candidates, BiFeO3 (BFO) has attracted much greater attention. BiFeO3 has long been known to be, in its bulk form, an antiferromagnetic, ferroelectric multiferroic [3,4] with antiferromagnetic Néel temperature (TN) of 643 K, and ferroelectric Curie temperature (TC) of 1103 K. In this work, we report on surface elemental analysis of unsputtered and sputtered (for depth profile analysis) bulk and thin films of BiFeO3 using x-ray photoelectron spectroscopy (XPS). The corresponding binding energies for Bi, Fe and O confirmed the phase purity of the bulk BiFeO3 compound. For the element Fe, the XPS spectrum was expanded from 700 to 740 eV. The 3/2 and 1/2 spin–orbit doublet components of the Fe 2p photoelectron were found to be located at 710.3 and 724.5 eV respectively. The XPS result showed single phase formation of BFO ceramic with a Fe3+ valence state. We do not find evidence for any Fe2+ impurities in the sample. From XPS spectra of the Fe 2p peaks for unsputtered and sputtered BFO thin films, the observed Fe 2p3/2 peak in both unsputtered and sputtered BFO thin films is found to be narrower and stronger than that of Fe 2p1/2 peak and the area of Fe 2p3/2 peak is greater than that of Fe 2p1/2 because of spin–orbit (j–j) coupling; Fe 2p3/2 has a degeneracy of four states whilst Fe 2p1/2 has only two. The binding energies of Fe 2p3/2 and Fe 2p1/2 obtained from the present study for unsputtered BFO films are 712.0 and 724.7 eV respectively and the satellite peak is not clearly distinguishable. However, the binding energies of Fe 2p3/2 and Fe 2p1/2 for sputtered BFO thin films were found to be 711.5 eV and 724.8 eV and, the satellite peaks of Fe 2p3/2 and Fe 2p1/2 were clearly distinguishable and do not overlap with either the Fe 2p3/2 or Fe 2p1/2 peaks. Based on this study, we conclude that phase pure, homogeneous BFO in both bulk and thin film form can be made easily using proper route/technique. The binding energies of the Fe 2p peaks in BFO thin films having high energy than that of its counter part of bulk BFO. More details will be presented and discussed.References: 1. N. A. Hill, J. Phys. Chem. B 104, 6694 (2000). 2. G. A. Smolenskii and I. E. Chupis, Sov. Phys. Usp., 25, 475 (1983). 3. S. V. Kiselev, R. P. Ozerov, and G. S. Zhdanov, Sov. Phys. Dokl., 7, 742 (1963).4. J. R. Teague, R. Gerson, and W. J. James, Solid State Commun., 8, 073 (1970).
10:30 AM - **G13.5
Giant Tunnel Electroresistance for Non-destructive Readout of Ferroelectric States.
Manuel Bibes 1 , Arnaud Crassous 1 , Vincent Garcia 1 , Ard Vlooswijk 3 , Gijsbert Rispens 3 , Laura Bocher 5 , Sergio Valencia 6 , Florian Kronast 6 , Shaima Enouz-Vedrenne 4 , Alexandre Gloter 5 , Dominique Imhoff 5 , Cyrile Deranlot 1 , Neil Mathur 2 , Beatriz Noheda 3 , Stephane Fusil 1 , Karim Bouzehouane 1 , Agnes Barthelemy 1
1 , Unite Mixte de Physique CNRS/Thales, Palaiseau France, 3 , University of Groningen, Groningen Netherlands, 5 , Laboratoire de Physique des Solides, Orsay France, 6 , Helmholtz-zentrum-Berlin, Berlin Germany, 4 , Thales Research and Technology, Palaiseau France, 2 , University of Cambridge, Cambridge United Kingdom
Show AbstractFerroelectrics possess a polarization that is spontaneous, stable and electrically switchable, and submicron-thick ferroelectric films are currently used as non-volatile memory elements (FeRAM) with destructive capacitive readout. Memories based on tunnel junctions with ultrathin ferroelectric barriers would enable non-destructive resistive readout. However, room-temperature polarization stability and switching at very low thickness is challenging. At room temperature, we use piezoresponse force microscopy to show robust ferroelectricity down to 1 nm in highly strained BaTiO3 films, and conductive atomic force microscopy to demonstrate the resistive readout of the polarization state via its influence on the tunnel current. The resulting electroresistance effect scales exponentially with the ferroelectric film thickness, reaching ~75000 % at 3 nm [1]. Our approach exploits the otherwise undesirable leakage current - dominated by tunneling at these very low thicknesses - to read the polarization state without destroying it. These results pave the way towards ferroelectric memories with simplified architectures, higher densities and faster operation, and should inspire further exploration of the interplay between quantum tunneling and ferroelectricity at the nanoscale. We will discuss the origin of the observed effects, their scalability and their extension to other ferroelectric materials. Finally, we will show that beyond their potential interest for future FeRAMs, ferroelectric tunnel barriers can bring exciting perspectives for spin-based memories (e.g. MRAMs) through the ferroelectric control of spin-polarization that we demonstrate in artificial multiferroic tunnel junctions. [1] V. Garcia et al, Nature 460, 81 (2009)
11:00 AM - G13: FeRAM-2
BREAK
11:30 AM - **G13.6
A Ferroelectric NAND Flash Memory for Low-power and Highly Reliable Enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V Low-power CPU and SoC.
Ken Takeuchi 1 , Teruyoshi Hatanaka 1 , Shuhei Tanakamaru 1 , Ryoji Yajima 1 , Shinji Noda 1 , Mitsue Takahashi 2 , Shigeki Sakai 2
1 Dept. of Electrical Engineering and Information Systems, University of Tokyo, Tokyo Japan, 2 , National Institute of Advanced Industrial Science and Technology, Tsukuba Japan
Show AbstractThis paper overview recent research results about ferroelectric FETs such as a Ferroelectric (Fe-) NAND flash memory for enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V operation low-power CPU and SoC.In the last five years, as the data through internet increases, the power consumption at the data center doubled. To solve the power crisis SSD is expected to replace HDD. For such an enterprise SSD, the Fe-NAND flash memory [1] is most suitable due to a low power consumption and a high reliability. The Fe-NAND is composed of Metal Ferroelectric Insulator Semiconductor transistors. The program/erase voltage decreases from 20V to 6V. In the Fe-NAND, the electric polarization in the ferroelectric layer flips with a lower electric field and the Vth of a memory cell shifts. Due to a low program/erase voltage, a low power operation is achieved. In the Fe-NAND, a high write/erase endurance, 100Million cycle, four orders of magnitudes higher than the conventional NAND, is realized because there is no stress-induced leakage current.The Fe-NAND flash memory with a non-volatile (NV) page buffer is also proposed [2]. The data fragmentation of SSD in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. In addition, a zero Vth memory cell scheme is proposed to best optimize the reliability of the Fe-NAND [3]. The Vth shift caused by the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. To realize a bit-by-bit verify and tighten the Vth distribution a negative word-line voltage step-down erase pulse scheme is proposed [4]. The negative word-line voltage erase accelerates the erase pulse ramp-up from 1ms to 2us. With the erase voltage that decreases by ΔVerase, the Vth shift is constant at 1/6ΔVerase. A 0.07V erase Vth distribution is achieved with ΔVerase of 0.4V. A 1.2V operation adaptive charge pump circuit for the low voltage and low power Fe-NAND is introduced [5]. By using Fe-FETs as diodes in the charge pump and optimizing the Vth of Fe-FETs at each pump stage, the power efficiency and the output voltage increase by 143% and 25% without the circuit area and process step penalty.Finally, a ferroelectric 6T-SRAM is proposed for the 0.5V operation low power CPU and SoC [6]. During the read/hold, the Vth of Fe-FETs automatically changes to increase the static noise margin by 60%. During the stand-by, the Vth increases to decrease the leakage current by 42%. As a result, the supply voltage by 0.11V, which decreases the active power by 32%. This work was partially supported by NEDO. [1] S. Sakai et. al., NVSMW&ICMTD, pp.103-105, 2008.[2] T. Hatanaka et. al., Symp. VLSI Circuits, pp.78-79, 2009.[3] T. Hatanaka et. al., ESSDERC, pp.225-228, 2009.[4] R. Yajima et. al., SSDM, pp.1196-1197, 2009.[5] S. Noda et. al., SSDM, pp.162-163, 2009.[6] S. Tanakamaru et. al., IEDM, 2009.
12:00 PM - G13.7
Fabrication of IGZO and In2O3-channel Ferroelectric-gate Thin Film Transistors.
Eisuke Tokumitsu 1 , Ken-ichi Haga 1 , Tomohiro Oiwa 1
1 Precision and Intelligence Lab, Tokyo Institute of Technology, Yokohama Japan
Show AbstractOxide-channel thin film transistors (TFTs) have attracted much attention for display applications and it would be interesting if we can realize high-density nonvolatile memories as well as logic circuits and driver TFTs by oxide-channel TFTs on a single substrate for future system-on-panel or system-on film applications. In this work, we have fabricated and characterized ferroelectric-gate TFTs using In-Ga-Zn-O (IGZO) or In2O3 as a channel material. The ferroelectric material used in this work is (Bi,La)4Ti3O12 (BLT). Bottom-gate structure TFTs were fabricated on SiO2/Si substrates using IGZO or In2O3 as a channel and BLT as a gate insulator materials, respectively. First, Pt/Ti or ITO layer was deposited by sputtering and patterned to form the bottom gate electrodes. Then, the ferroelectric BLT thin film was deposited by the sol-gel technique with a crystallization temprature of 750C. The thickness of the BLT film is approximately 200 nm. Then, thin (10-20nm) IGZO or In2O3 channel layer was deposited by sputtering. The deposition conditions such as O2/Ar ratio were adjusted to obtaine a carrier concentration of about 10^18 cm-3 for both IGZO and In2O3. Next, source and drain electrodes were deposited and the device was isolated by the dry etching technique. The channel length and width are typically 10 and 100 μm, respectively.We observed normal n-channel transistor operation for both IGZO and In2O3-channel TFTs. When the IGZO film was deposited at room temperature, a charge injection type hysteresis was observed in drain current – gate voltage (ID-VG) characteristics. Post fabrication anneal at 300C reduced the charge-injection-type hystereesis and the subthreshold swing was also improved from 0.27 to 0.19 V/decade. However, non-volatile memory effect due to the ferroelectric BLT gate insulator was not observed. On the other hand, when the In2O3 was used as a channel, a hysteresis loop due to the ferroelectric gate insulator was clearly observed in ID-VG characteristics. A memory window of 2V, a subthreshold voltage swing of 0.2V/decade, a field-effect mobility of 6.3 cm2/Vs, and a on/off drain current ratio of more than 10^5 were obtained.
12:15 PM - G13.8
Transparent Photo-stable ZnO Non-volatile Memory Transistor With Ferroelectric Polymer.
Chan Ho Park 1 , Seongil Im 1 , Jungheum Yun 2 , Gun Hwan Lee 2 , Byoung Hun Lee 3 , Myoung Mo Sung 3
1 Institute of Physics and Applied Physics , Yonsei University , Seoul Korea (the Republic of), 2 Department of Surface Technology, Korea Institute of Material Science, Changwon Korea (the Republic of), 3 Department of Chemistry, Hanyang University, Seoul Korea (the Republic of)
Show AbstractFerroelectric field effect transistors (FeFETs) have been extensively studied as a non-volatile memory (NVM) device particularly for Si-based circuits in the past, even though they have some disadvantages due to the depolarization problems originating at the ferroelectric/semiconductor interface. Recently, these FeFET approaches shifted to organic or oxide thin-film transistor (TFT) electronics adopting plastic and glass substrates, since poly(vinylidene fluoride/trifluoroethylene) [P(VDF/TrFE)] copolymer has been found as an accommodating ferroelectric polymer with an induced remnant polarization of ~10 μC/cm2, short switching time of ~1 ms, and ease to fabricate by solution process at low temperature.Transparent oxide TFTs are to be used as functional devices in the coming ubiquitous technology era as well as a practical transparent pixel driver in the present. And transparent NVM and logic devices are very necessary if we aim at various transparent device applications. Transparent complementary inverters and NVM resistors were recently reported but transparent NVM-TFT with good write/erase capability has rarely been investigated (except the one with charge injection type memory, which showed a serious limit in erase). The most challenging in the present memory TFT fabrication was how to deposit a transparent conducting gate oxide on top of the ferroelectric P(VDF/TrFE) without any damage or any property change of the polymer, which might be unavoidable under plasma process. Regardless of some damage or change of ferroelectric polymer, our transparent or semi-transparent NVM-TFTs demonstrate promising results in respects of the retention time and memory window although those properties appeared somewhat inferior if compared to the performances of opaque NVM-TFTs with Al-evaporated electrodes.Our previous work reported on ZnO-based ferroelectric NVM-TFTs with a nano-meter thin Al2O3 layer inserted between the ferroelectric P(VDF/TrFE) and ZnO channel, exhibiting relatively a good memory window and improved retention properties as well. In the present work, we report on the fabrication of transparent top-gate ZnO non-volatile memory thin-film transistors (NVM-TFTs) with 200 nm-thick P(VDF-TrFE) ferroelectric layer; semi-transparent 10 nm-thin AgOx and transparent 130 nm-thick indium-zinc-oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by RF sputtering. Our semi-transparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±60 V for WR and ER states. Both devices stably operated under visible illuminations.
12:30 PM - G13.9
Atomic Layer Deposition of Pb(Zr,Ti)Ox/Al2O3 Ultrathin Films on 4H-SiC.
Feng Zhang 1 , Ya-Chuan Perng 1 , Jane P. Chang 1
1 Department of Chemical and Biomolecular Engineering, University of California, Los Angeles, Los Angeles, California, United States
Show AbstractLead zirconate titanate Pb(Zr,Ti)Ox (PZT) has been extensively studied and already applied in ferroelectric random access memories (FeRAM) due to its excellent ferroelectric property, high dielectric constant and good stability. While atomic layer deposition (ALD) is a low throughput process compared to the current chemical vapor deposition (CVD), it offers a distinct advantage in synthesizing PZT films, especially in terms of compositional/structural control and deposition uniformity and conformality. In this work, our PZT films are synthesized using an ALD process to deposit a PbO-ZrO2-PbO-TiO2 layered structure. The precursors and oxidant used in this work were Lead bis(2,2,6,6-tetramethyl-3,5-heptanedionato) (Pb(C11H19O2)2),Titanium, diisopropoxide bis(2,2,6,6-tetramethyl-3,5-heptanedionate) (Ti(OC3H7)2(C11H19O2)2), Zirconium chloride (ZrCl4) and H2O, respectively. The deposition rate for PZT is about 0.7 nm/cycle-sequence. According to the results on inductively coupled plasma-mass spectroscopy (ICP-MS) and X-ray photoelectron spectroscopy (XPS), the composition ratio of Pb, Zr, and Ti was near to 2:1:1 and in agreement with the stoichiometry of the deposition sequence. To assess the effectiveness of PZT for metal-ferroelectric-insulator-semiconductor (MFIS) transistor application, ultrathin films of PZT/Al2O3 (14/12 nm) were deposited on 4H-SiC substrates and then annealed at 900-1000°C in N2. The (002) peak of PZT was found to have the highest X-ray diffraction (XRD) intensity, which agrees with the crystal structure based on the specific deposition sequence. The polarization property was found in the P-V measurement with the remanent polarization (2Pr), saturation polarization (2Ps), and coercive field (2Ec) to be 7 μC/cm2, 14 μC/cm2 and 160 kV/cm, respectively. Meanwhile, the clockwise hysteresis loops appeared in the C-V response with a flatband voltage shift of about 6 V, which indicates a total charge quantity of 0.56 μC/cm2, less than 1/10 of remanent polarization, in the PZT/Al2O3 films. This means the charges in the PZT/Al2O3 films did not greatly affect the polarization of the PZT devices.
12:45 PM - G13.10
Ferroelectric Properties of Pt/Pb(Zr, Ti)O3/Al2O3/ZnO/Pt Stack Capacitors for Nonvolatile Memory Applications.
Min Hyuk Park 1 2 , Hyun Ju Lee 1 2 , Cheol Seong Hwang 1 2
1 Department of Material Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show Abstract Pt/PZT/Pt (MFM), Pt/PZT/Al2O3/Pt (MFIM), and Pt/PZT/Al2O3/ZnO/Pt (MFISM) stack capacitors with ZnO semiconducting layer were fabricated and their electrical properties were examined. Although the electrical characteristics of the MFM and MFIM structure was not different from expectation, MFISM capacitors without patterning the semiconducting ZnO layer showed quite abnormal ferroelectric P-V hysteresis behavior. The abnormal hysteresis loops of MFISM capacitors could be originated from large leakage current through the insulating F-I layer. However, the MFISM capacitors showed low leakage current level similar to that of the other capacitors. This suggests that there were other reasons for the unusual P-V hysteresis loop. The MFISM capacitors showed two unusual characteristics: one is the asymmetry with respect to the bias voltage of hysteresis loop and the other is unreasonably high polarization value. The first can be understood from the rectifying nature of the ZnO/Pt interface. The second was understood by considering the P-V measurement proto call of the TFA 2000 (aixacct systems, Germany) and the behavior of the carriers in the stacked capacitor. Before measurement, ferroelectric layer was pre-poled upward and accumulation layer was formed on ZnO/PZT interface. Due to Schottky nature of ZnO/Pt interface, depletion layer was formed near a selected Pt top electrode (TE). As positive bias increases, depletion width decreases and carrier density increases in the region near TE. Due to higher carrier density and shorter distance from TE, lower voltage is applied to the ZnO layer near TE and polarization switching occurs under relatively lower voltage. After that, as the positive bias increases, the polarization switching propagates into a wider area. All the carriers in the ZnO layer with a sample area of 2 cm2 eventually pass through the 0.0005 cm2 area of ZnO/Pt interface. This phenomenon seems to be similar to the erase mechanism of the flash memory, by which a number of cells in a block are erased simultaneously. By using partially patterned channel area, simultaneous erase of a wide area by applying gate voltage would be possible. To demonstrate that the hypothesis is correct, the ZnO layer which was uncovered by the Pt TE was etched using 1 % HCl solution and the P-V hysteresis of the capacitors was measured again. The P-V hysteresis loop of the two MFISM capacitors with 5 and 20nm-thick ZnO layer became much normal. In this study, P-V and I-V characteristics of MFM, MFIM and MFISM capacitors were reported. The unusual P-V characteristics of MFISM capacitors could be understood by considering the P-V measurement ptoro call of TFA2000, the electrical band structure and resulting behavior of the carriers of the stacked MFISM capacitors. Current response to voltage pulse of the MFISM capacitor can be used as the novel mechanism of erase for the flash-like structure of FeFET cell array by adopting partially patterned channel layer.
G14/H7: Joint Session: Applications II
Session Chairs
Thursday PM, April 08, 2010
Room 2011 (Moscone West)
2:45 PM - **G14.1/H7.1
Phase Change Based Memory Devices: Characteristic Behaviors, Physical Models and Key Materials Properties.
Ilya Karpov 1 , DerChang Kau 1 , Gianpaolo Spadini 1 , David Kencke 1
1 , Intel Corporation, Santa Clara, California, United States
Show AbstractPhase Change Memory (PCM) is based on electrically initiated reversible amorphous-to-crystalline phase changes in chalcogenide materials, such as Ge2Sb2Te5 (GST) [1]. We present device characteristics, IV and programming curves, of phase change based memory devices [1,2] and their relation to the device performance. Then we show the results of the studies of the device temporal dependencies, in short and long time scales. We analyze phenomena affecting programming and read such as threshold switching, noise and drift [3,4]. After the data and corresponding models are discussed we identify key materials parameters affecting device performance including variability. Finally we consider how the devices behavior changes with scaling including effects of interfaces such as electrical and thermal resistances [5]. References: [1] S. Lai and T. Lowrey, IEDM Tech. Dig., p.803, 2001.[2] B. Johnson and S. Hudgens, MRS Bulletin, V29, No. 11, p. 829, 2004.[3] I. Karpov, D. Kau, G. Spadini, V. Karpov, Non-Volatile Memory Technology Symposium, p. 1, 2008. [4] M. Nardone, V. I. Kozub, I. V. Karpov, and V. G. Karpov, Phys. Rev. B 79, 165206, 2009.[5] D. Kencke, I. Karpov, B. Johnson, S. Lee, D. Kau, S. Hudgens, J. Reifenberg, S. Savransky, J. Zhang, M. Giles, G. Spadini, IEDM Tech. Dig., p.323, 2007.
3:15 PM - G14.2/H7.2
PCRAM Performances Improvement With Nitrogen Doped GeTe Material for Embedded Applications.
Emmanuel Gourvest 1 2 , Christophe Vallee 2 , Frederic Fillot 3 , Herve Roussel 4 , Luca Perniola 3 , Andrea Fantini 3 , Jean-Claude Bastien 3 , Audrey Bastard 1 3 , Sebastien Loubriat 3 , Anne Roule 3 , Sandrine Lhostis 1 , Sylvain Maitrejean 3
1 , STMicroelectronics, Grenoble France, 2 LTM, CNRS/UJF/INPG, Grenoble France, 3 LETI-Minatec, CEA, Grenoble France, 4 LMGP, CNRS/INPG, Grenoble France
Show AbstractChalcogenide materials are widely used for phase-change data storage based on their high transformation speed between their highly electrically contrasted crystalline and amorphous phase. High temperature applications require moreover high retention time, i.e. stable amorphous phase, at working temperature. Binary compound GeTe have attracted great attention for such applications since it presents high phase transition temperature and good endurance. Improvement of data retention [1] - 10 years at 110°C compared to 10 years at 70°C for conventional Ge2Sb2Te5 - was estimated but keeps out of higher temperature applications specifications. Furthermore it has been shown in a previous work [2] thermal instability of non-stoichiometric GeTe films with post-crystallization of germanium excess. Recently, different works [3-4] related that nitrogen doping favourably modifies crystallization properties of Ge2Sb2Te5 at high temperature. In this study we investigated the influence of nitrogen doping on performance of GeTe thin films. Optical phase-change properties were measured for various nitrogen doped GeTe films and showed significant increase of crystallization temperature and data retention - up to 10 years at 145°C - compared to GeTe ones. Work especially focused on the understanding of the role of nitrogen on crystallisation process using X-ray Photoelectron Spectroscopy (XPS) and X-Ray Diffraction (XRD). XPS evidenced nitrogen bonding with germanium. For nitrogen doped-Ge rich GeTe films, no post-crystallization of germanium excess was detected by XRD after annealing. These results suggest the formation of Ge-N amorphous phase. Concerning crystal microstructure, crystallite sizes decrease from 40 nm down to 16 nm when nitrogen content increases. Moreover, evolution of stress-free lattice parameter with nitrogen doping was observed. Based on these characterizations, crystallisation mechanisms can be discussed. Additionally, nitrogen-doped GeTe films were integrated in simple test devices on 200 mm wafers. Electrical characteristics showed three orders of magnitude in resistance between amorphous (RESET) and crystalline (SET) states for electrical stress pulse down to 25 ns and a good endurance. This study showed nitrogen-doped GeTe material is a very promising candidate to meet technological requirements for PCRAM high temperature applications. [1] A. Fantini et al. IEEE Proceedings of IMW (2009) pp.66-67. [2] E. Gourvest et al. Appl. Phys. Lett. 95, 1 (2009). [3] S. M. Kim et al. Thin Solid Films 469-470 (2004) 322-326. [4] R. M. Shelby and S. Raoux J. Appl. Phys. 105, 104902 (2009).
3:30 PM - G14.3/H7.3
Electromigration in GeSbTe-based Chalcogenide Materials Under Pulsed DC for Set-stuck Failure.
Tae-Youl Yang 1 , Ju-Young Cho 1 , Young-Chang Joo 1
1 Department of materials science and engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractPhase change memory made rapid progress towards commercializing, but the lack of accurate mechanism of reliability-degradation remains as one of the most significant unsolved problem. In endurace reliability issues, set-stuck is one of the typical failures. This failure is that cell resistance fixed at the set-state, and is caused by the compositional change of Ge2Sb2Te5 due to electric-field-enhanced mass flow during the reset operations. In molten Ge2Sb2Te5, Ge and Sb atoms migrated to the cathode, whearas Te atoms migrted to the anode under electrical bias. This compositional change is induced by the electrostatic-force-induced electromigration. However, the results of the previous study are not enough to predict the failure in real cell because atomic flux cannot be quantified. Study on the inhibition of electromigration based on the understanding of failure mecahnism is required to solve the reliability problem. In this study, we quantified the flux of the constituent elements in the electromigration of molten Ge2Sb2Te5, and confimed the driving force by comparion with the electromigration behavior in molten GeTe and Ge15Sb85. In addition, we also investigated the electromigration suppression by N-doping in Ge2Sb2Te5. Isolated line structure was used for a simple and systematic study on the electromigration. The line was isolated by Mo contact pads to prevented artifacts from a large source/sink of diffusing atoms. Nitrogen was doped in Ge2Sb2Te5 with 3 at.% by N2 gas flowing during the deposition. Electrical bias was applied to the line using DC-type pulse of 7~10 V with long period (~ 10-3 s) enough for the melting by Joule heating. Compositional variation was detected by WDS. Compositional variation by the electromigration was observed as a function of diffusion time in the molten Ge2Sb2Te5. Interdiffusion of Sb and Te atoms occurred prior to the diffusion of Ge atoms. In the comparison of the number of migrated atoms normalized by the initial number concentration, Sb showed the fastest diffusion velocity. The DZ*, which is the parameter for diffusion rate, of Ge, Sb, and Te was calculated from the number of migrated atoms to be 1.13. 1.98, and -1.17 × 10-5 cm2 s-1, respectively. Z* values are also calculated to be 0.28, 0.38, and -0.29. In the electromigration of molten GeTe, we observed the elemental separation into Te at the anode and Ge near at the cathode. However, elemental separation toward the electrodes was not occurred in moltne Ge15Sb85. Based on the results, we confirmed that driving force of the electromigration is the electrostatic-force into each element. In addition, we observed that compositional change by the electromigration was suppressed in the N-doped Ge2Sb2Te5 line. The DZ* values in N-doped Ge2Sb2Te5 will be also calculated by the control of diffusion time. N-doped Ge2Sb2Te5 is expected to retard the endurance failures because the doping increases the viscosity of materials, and decreases the mobility of atoms.
3:45 PM - G14.4/H7.4
Structural and Electrical Switching Dynamics in Phase-change Random Access Memory.
Jasper L. Oosthoek 1 2 , Frans Voogt 3 , Bart Kooi 1 2
1 Zernike Institute for Advanced Materials, University of Groningen, Groningen Netherlands, 2 , Materials Innovation Institute (M2i), Delft Netherlands, 3 Process and Material Analysis, NXP Semiconductors, Nijmegen Netherlands
Show AbstractPhase-change materials, such as Ge2Sb2Te5, have been developed for rewritable CD and DVD applications and are currently intensively studied for future optical and electrical non-volatile memories. Both the technology and also the science of phase-change materials have shown important progress but still offer challenges.The main focus of the presentation will be on the electrical characterization of so-called phase-change line cells. Currently, these memory cells can be switched ~10^8 times before break down, clearly sufficient for replacement of Flash memory. Particular attention is paid to the evolution of the cell properties with the number of switching cycles and to data retention. Interesting cell properties include the temporal drift of the amorphous resistance and the required (minimum) threshold voltage for the amorphous to crystalline phase change. A mechanism is put forward that explains the degradation of the line cells with switching cycles towards the situation that the cell is stuck in the crystalline state.Apart from electrical characterization also crystallization studies will be presented of both phase change thin films and line cell devices based on in situ Transmission Electron Microscopy. A final aim of our work is to combine nano-second switching and electrical characterization with nano-scale imaging of the line cells in the electron microscope.
G15: PCRAM
Session Chairs
Yoshihisa Fujisaki
Maria Mitkova
Thursday PM, April 08, 2010
Room 2011 (Moscone West)
4:30 PM - **G15.1
Material Perspectives for Phase Change Memories: The Role of Chemical Composition, Deposition Method, and Interfaces on the Thermal Properties of the Chalcogenide Material and of its Interfaces.
Claudia Wiemer 1
1 Laboratorio MDM, CNR-INFM, Agrate Brianza, Mi, Italy
Show AbstractThe optimization of phase change memory devices requires a compromise between reducing element sizes and maintaining data retention and reliability. Investigating new chalcogenide materials in terms of electrical performances cannot proceed without the knowledge of fundamental properties, like electron and hole mobilities, thermal conductivity, electrical resistivity and thermal stability, together with the increased control of their interface with the other elements of the cell. On the other hand, in order to fill aggressive high aspect ratio structures, deposition methods alternative to physical vapor deposition should be investigated. In this presentation, the techniques for measuring the thermal conductivity are shortly reviewed, along with the recent advances in metal organic chemical vapor deposition (MOCVD) of chalcogenide materials. In particular, growth studies were aimed to the optimization of thermal, N2-based MOCVD of Ge-Sb-Te thin layers on flat SiO2/Si and patterned substrates. Ge2Sb2Te5 hcp layers were deposited by the use of a Ge catalyst layer. The obtained Ge-Sb-Te alloys exhibited up to 10 phase switching cycles upon laser irradiation; Ge-rich alloys were conformally deposited into sub-micron trenches coated by a Ge layer. MOCVD was also successfully employed for the growth of Ge-Sb-Te crystalline Nano Wires (NWs).Since most of the work performed in material characterization proceeds on flat, polycrystalline layers, special attention is devoted to the effects of size, preferential orientation and interfaces on the quantification of thermal and electrical properties. The effect of the deposition method on the characteristics of Ge2Sb2Te5 and alternative chalcogenide materials will be also discussed. A more accurate definition of the material characteristics is therefore proposed, allowing the optimization of the inputs for modeling innovative phase change memory devices.
5:00 PM - G15.2
Nonvolatile Floating Gate Memory Devices Containing AgInSbTe-SiO2 Nanocomposite Thin Film Prepared by Sputtering Method.
Kuo-Chang Chiang 1 , Tsung-Eong Hsieh 1
1 Materials Science and Engineering, National Chiao Tung University, Hsinchu Taiwan
Show AbstractNonvolatile floating gate memory (NFGM) devices with metal-oxide-semiconductor (MOS) structure containing AgInSbTe (AIST)-SiO2 nanocomposite layer were prepared by sputtering method and their memory effects were investigated by capacitance-voltage (C-V) measurement, x-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM). The retention times of devices were also measured so as to evaluate the feasibility of AIST-SiO2 nanocomposite layer to NFGM applications.As-deposited sample exhibited a hysteresis memory window (ΔVFB) shift = 2.65V and charge density = 2.39×1012 cm^-2 after ±8V gate voltage sweep. As to the 400οC-annealed sample, significant ΔVFB shift = 5.91V and charge density = 5.22×1012 cm^-2 after 8V sweeping were observed. The enlargement of ΔVFB shift was ascribed to the electron trapping as well as the hole trapping in the nanocomposite layer rather than the interface traps. Cross-sectional TEM revealed that the nanocomposite layer contains the crystalline AIST nanoparticles with sizes about 5 to 7 nm embedded in SiO2 matrix and, with the aid of energy dispersive spectrometer (EDX) analysis, the main phase type in AIST nanoparticles was found to be Sb2Te. XPS analysis indicated that post-annealing treatment causes the reduction of In and Sn oxides to form more metallic phases in nanocomposite layer. This provides more charge storage traps in the device and thus improves its non-volatile memory effects. Retention time analysis revealed a memory window shift about 3.50V and the charge loss about 28.4% in the sample after 10^4 sec retention time test. In addition to the distinct physical properties, above results also show that the utilization of AIST-SiO2 nanocomposite layer is able to simplify the device structure. This illustrates the promising applications of AIST-SiO2 nanocomposite layer in NFGM devices.
5:15 PM - G15.3
Improved Thermal Behaviour of the GaSb-GeTe Quaternary Phase Change Material for PCRAM Applications.
Sandrine Lhostis 1 2 , Edrisse Arbaoui 1 2 , Audrey Bastard 1 2 , Pierre-Eugene Coulon 3 , Caroline Bonafos 3 , Berangere Hyot 2 , Sylvie Favier 2 , Andrea Fantini 2 , Luca Perniola 2 , Sebastien Loubriat 2 , Anne Roule 2 , Marilyn Armand 2 , Alain Fargeix 2 , Sylvain Maitrejean 2 , Veronique Sousa 2
1 , STMicroelectronics, Crolles France, 2 , CEA, LETI, MINATEC, Grenoble France, 3 , CEMES, Toulouse France
Show AbstractChalcogenide materials like the well known GeSbTe (GST) family are widely studied for their application in Phase Change Random Access Memory (PCRAM). The standard composition Ge2Sb2Te5 suffers from a too low retention time at temperatures as high as 150°C, which can be a limiting factor depending on the targeted application. We have already presented interesting properties for the GeTe compound [1] with a crystallization temperature as high as 185°C and 10 years retention time at 110°C. Enhanced properties were also reported with the introduction of GaSb in SbTe [2] with best properties for 25% Ga in GaSbTe. We present here the study of the quaternary GaSb-GeTe thin films that can be seen as Ga introduction in GST materials. The crystallization temperatures and activation energies are fully investigated and are found to increase with the GaSb concentration. Interesting composition with a crystallization temperature as high as 350°C is obtained. We observe segregation during crystallization depending on the thin film composition. A detailed study on the crystalline phases and the chemical composition of the layer is performed through High Resolution Transmission Electron Microscopy (HREM) coupled to Electron Energy Loss Spectroscopy in scanning mode by using a nanometer probe (STEM-EELS). We correlate our chemical-physical characterizations to electrical measurements on the GaSb-GeTe materials integrated in a simple memory cell.[1] A. Fantini et al. IEEE Proceedings of IMW pp.66-67 (2009).[2] H.Y. Cheng et al., Thin Solid Films 516 p. 5513 (2008).
5:30 PM - G15.4
Colloidal GeTe Nanocrystals With Ambient-temperature Polar Ordering for Self-assembled Nonvolatile Memories.
Mark Polking 1 , Haimei Zheng 2 3 , Jeffrey Urban 4 , Delia Milliron 4 , Emory Chan 4 , Marissa Caldwell 5 , Simone Raoux 6 , Christian Kisielowski 3 , Joel Ager 7 , Ramamoorthy Ramesh 1 7 , Paul Alivisatos 2 7
1 Department of Materials Science and Engineering, University of California, Berkeley, Berkeley, California, United States, 2 Department of Chemistry, University of California, Berkeley, Berkeley, California, United States, 3 National Center for Electron Microscopy, Lawrence Berkeley National Laboratory, Berkeley, California, United States, 4 The Molecular Foundry, Lawrence Berkeley National Laboratory, Berkeley, California, United States, 5 Department of Chemistry, Stanford University, Stanford, California, United States, 6 , IBM T. J. Watson Research Center, Yorktown Heights, New York, United States, 7 Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California, United States
Show AbstractBoth ferroelectrics and phase-change materials have emerged as leading candidates for the next generation of nonvolatile data storage media. Practical application of the former class of materials in FeRAM devices, however, demands ambient-temperature stability of the polar phase at the nanoscale. The question of polar phase stability in low-dimensional nanomaterials has long remained elusive: While theoretical reports have indicated the stability of polar ordering in perovskite nanodots down to length scales of a few nanometers, experimental evidence of polar phase stability in low-dimensional nanomaterials is noticeably lacking. Here, we employ colloidal chemistry techniques for the first size-controlled solution-phase synthesis of a polar nanomaterial, the IV-VI semiconductor germanium telluride, and provide clear experimental evidence for polar phase stability in these nanocrystals down to the sub-5 nm length scale. The ambient-temperature stability of polar ordering in such solution-processible nanomaterials offers the possibility of nonvolatile memories with Tbit/in2 densities that may be fabricated using self-assembly techniques. GeTe, also a promising material for phase-change memory applications, undergoes a spontaneous structural distortion from a centrosymmetric cubic phase to a polar phase through a rhombohedral angular distortion of the unit cell and a relative displacement of the Ge and Te sublattices that removes the inversion symmetry. To explore the stability of this polar phase, nearly monodisperse GeTe nanocrystals with average diameters of 8, 17, 100, and 500 nm were prepared. Direct experimental evidence of a stable ferroelectric distortion in these nanocrystals down to at least 5 nm in diameter at ambient temperature was obtained using aberration-corrected transmission electron microscopy with sub-Ångstrom resolution. Exit-wave reconstruction of image series enabled the direct confirmation of an angular distortion of approximately 1.1 degrees and a relative sublattice displacement of around 0.2 Å in individual 4.5-8 nm GeTe nanocrystals. In addition, a size-dependent polar phase transition was observed in nanocrystals of all sizes with in situ temperature-dependent synchrotron x-ray and Raman scattering measurements. Analysis of powder x-ray diffraction spectra by Rietveld refinement revealed a monotonic decrease in the magnitude of the rhombohedral angular distortion with decreasing particle size. Further, these measurements confirmed the room-temperature stability of the polar phase and demonstrated a reversible displacive ferroelectric phase transition at temperatures exceeding 150 degrees Celsius for all particle sizes.
G16: Poster Session: FeRAM III
Session Chairs
Yoshihisa Fujisaki
Eisuke Tokumitsu
Friday AM, April 09, 2010
Salon Level (Marriott)
9:00 PM - G16.2
Effect of W Substitution in Strontium Bismuth Tantalate Ferroelectric Ceramics: Enhanced Ferroelectric Properties.
Indrani Coondoo 1 , Ashok Biradar 1 , Arun Jha 2
1 , National Physical Laboratory, New Delhi, Delhi, India, 2 , Delhi Technological University, Delhi, Delhi, India
Show AbstractFerroelectrics are exceedingly useful materials in modern technology, with applications as transducers, actuators, dielectrics, and nonvolatile memories. Among ferroelectrics, it was found that bismuth oxide layered structures (e.g. SrBi2Ta2O9, BaBi2Ta2O9, SrBi2Nb2O9) originally synthesized by Aurivillius are the most suitable ones for NvRAMs. Since Araujo et. al. reported the fatigue free behavior of SrBi2Ta2O9 (SBT), it has occupied an important position in Pb-free piezoelectrics as well as realization of ferroelectric nonvolatile memories (Fe-RAM).The crystal structure of SBT consists of (Bi2O2)2+ layers and perovskite-type (SrTa2O7)2- units with double TaO6 octahedral layers. One interesting feature of the Aurivillius phases resides in the compositional flexibility of the perovskite blocks which allows incorporating various cations for the A-site and B-site. It is thus possible to modify the ferroelectric properties according to the chemical composition. The ferroelectricity arises mainly in the perovskite blocks; the ferroelectricity is attributed to the rotation and tilting of TaO6 octahedra as well as the off-center displacement of Ta ions in the octahedral unit in SBT.Here we report the influence of tungsten (W) substitution in SBT on crystal structure, dielectric properties and ferroelectric properties. The sintering temperature was optimized to obtain better structural and electrical properties. Tungsten-doped SBT ceramics [SrBi2(Ta1-xWx)2O9 ; 0.0 ≤ x ≤ 0.20] were synthesized by solid state reaction method using different sintering temperatures (1100 οC, 1150 οC, 1200 οC and 1250 οC). The room temperature structures of the samples were determined by means of powder X-ray diffraction. XRD of the samples reveal that the single phase layered perovskite structure is maintained in the samples with tungsten content x ≤ 0.05. W doping is found to significantly affect the structural and electrical properties of SBT, including lattice parameters, dielectric permittivity, Curie temperature, and ferroelectricity. Tungsten doping is effective in enhancing the dielectric properties. Dielectric constant (ε) and the Curie temperature (Tc) increases with increasing W content. The dielectric loss reduces significantly with increase in W doping level. The maximum Tc of ~ 390 οC is observed in the sample with x = 0.20 as compared to ~ 320 οC for the undoped sample when sintered at 1200 οC. The peak ε increases from ~ 270 in the sample with x = 0.0 to ~ 700 for the composition with x = 0.20, when sintered at 1200 οC. All the tungsten-doped ceramics have higher 2Pr than that in the undoped samples. The maximum 2Pr (~25 μC/cm2) is obtained in the composition with x = 0.05 sintered at 1200 οC. These effects have been interpreted based on the model of the recovery of oxygen vacancies upon W doping. Such compositions with low loss and high Pr values should be excellent materials for highly stable ferroelectric memory devices.
9:00 PM - G16.3
Crystal-structure and Dielectric Properties of La and Nd Codoped Multiferroic BiFeO3 Ceramics.
Carlos Ostos 1 , Oscar Raymond 1 , Jesus Siqueiros 1 , Xavier Vendrell 3 , Nelson Suarez-Almodovar 2 , Lourdes Mestres 3
1 Advanced Materials, UNAM, Ensenada, BC, Mexico, 3 Inorganic Chemistry, University of Barcelona, Barcelona, Catalonia, Spain, 2 Physics, Universidad de la Habana, La Habana, LH, Cuba
Show AbstractMultiferroic materials have coexisting ferroelectric and magnetic orders, which endow materials with an additional degree of freedom to be used as actuators, sensors and storage devices. BFO is reported to be a rhombohedrally distorted perovskite at room temperature, and ferroelectric and antiferromagnetic below 1100 K and 640 K respectively [1]. Unfortunately, BiFeO3 has poor ferroelectric performance due to severe electric leakage both in thin films and in the bulk, and pure samples are difficult to obtain without the presence of ternary oxides such as Bi25FeO39 and Bi2Fe4O9 [2-3]. It is believed that electrical leakage is caused by oxygen vacancies and iron ions with different valences via the formation of shallow energy centers. Partial substitution of bismuth by rare-earth elements is a feasible way to stabilize the BFO phase [4] and, in order to overcome the leakage problems, the resistivity of BFO can be controlled by donor doping [5]. In this work, simultaneous partial substitutions of bismuth by lanthanum in the A-site and iron by niobium in the B-site of the perovskite structure were chosen as means to enhance the stability and impro
9:00 PM - G16.5
Highly Oriented Single Phase Multiferroics for Nonvolatile Memory.
Dilsom Sanchez 1 , Ashok Kumar 1 , Ram Katiyar 1
1 Physics, University of Puerto Rico, Rio Piedras campus, San Juan , Puerto Rico, United States
Show AbstractMagneto electric (ME) multiferroic (MF) materials that couple with the electric and magnetic fields possess a rich variety of microscopic, mesoscopic and macroscopic properties. For example, it is possible to manipulate the electrical state of a multiferroic material through a magnetic field or vice versa, which is not only appealing scientifically, but also makes the multiferroic materials promising for a wide range of applications, including electrically controlled microwave phase shifters or ferromagnetic resonance devices, magnetically controlled electro-optic or piezoelectric devices, broadband magnetic field sensors, and magnetoelectric memory cells.Highly oriented single phase MF thin films of Pb(Zr0.53Ti0.47)1-x (Fe0.50 Ta0.50)xO3 (PZFT) (x= 0.10, 0.20, 0.30, 0.40) were fabricated by pulse laser deposition technique (PLD). Surface topography of these films showed well defined grain with average grain size ~ 20 -100 nm, the grain size increases with increase in Ta and Fe compositions. The surface roughness (~ 2-8 nm) also increases with increase in Fe and Ta compositions. X-ray diffraction pattern confirmed (100) orientations of these films without any pyrochlore/impurity phase. All of these films indicated low dielectric loss, low leakage current, and high dielectric constant. The dielectric constant maximum temperature shifted to lower temperature with increase in iron and tantalum concentrations. The magnetization vs. applied magnetic field (M-H) curves showed well defined hysteresis with remanent magnetization (Mr ~ 0.004- 0.13 emu/gm) and very small coercive field (900 Oe). The AC and DC conductivities of PZTFT showed very low conductivity (~ 10-9 to 10-7 S/cm-1) at room temperature. These films displayed very high polarization ~ (60- 75 µC/cm2) at room temperature and therefore these may be suitable for high density non volatile memories. Ferromagnetic and ferroelectric behavior of these films will be discussed for high k coated Si based substrate.
9:00 PM - G16.6
Multiferroic Properties in ZnO:(Cr,Ti) Thin Films Prepared by r.f. Magnetron Sputtering.
Youngmin Lee 1 , Sejoon Lee 2 , Yoon Shon 2 , Han Tae Ryu 1 , Deuk Young Kim 1
1 Semiconductor science, Dongguk University, Seoul Korea (the Republic of), 2 Quantum-functional Semiconductor Research Center, Dongguk University, Seoul Korea (the Republic of)
Show AbstractThe multiferroic ZnO:(Cr,Ti) thin films were prepared by co-sputtering of ZnO:Cr (Cr ~1 at.%) and Ti using r.f. reactive magnetron sputtering and d.c. magnetron sputtering, respectively, and their surface, structural, vibrational, magnetic, and electrical properties were investigated. For measurements of scanning electron microscopy, a local agglomeration of crystal grains, which might be caused from the formation of Zn1-x-yCrxTiyO solid solutions, were observed when the Ti contents were increased. The films were confirmed to have a c-axis-preferential wurtzite lattice structure, and for the samples containing the Ti contents of 0.2 ~ 0.3 at.%, the Bragg's angle was observed to shift to the lower angle region because of the lattice expansion due to the incorporation of Ti2+ ions, which have larger ionic radius (0.86 Å) than Zn2+ (0.74 Å), into Zn2+ sites. However, the samples containing the Ti contents over 0.4 at.% showed the phase segregation with exhibiting the shift of Bragg's angle to the larger angle region due to the interstitially- incorporated Ti ions. These results indicated that the solution limit of Ti co-dopants into Cr-doped ZnO is ~ 0.3 at.%. The incorporation of Ti additives was observed to directly affect the magnetic properties of the samples. After Ti-co-doping, the remnant magnetization was increased by two times compared with samples with no Ti co-dopants. This result is attributed to the decrease of molecular free-energy resulting from the increased magnetic moments, which are supplied from two spins in d-orbital of Ti2+(3d24s0). However, the coercive magnetic field was observed to be decreased due to the degraded magnetic anisotropy, which is caused by the lattice displacement due to the incorporation of Ti foreign atoms. Ti co-dopants incorporated into Cr-doped ZnO thin films were observed also to strongly affect the ferroelectric properties of the samples. For samples co-doped with Ti additives, the remnant polarization was observed to be considerably increased by approximately ten times compared to samples with no Ti additives. This result is attributed to the increased symmetrical molecular-field due to the increased local lattice displacements. However, the coercive electric field was observed to be monotonically decreased with increasing Ti contents. This result is considered as resulting from the formation of leakage channels which might be constructed with morphologically-localized Ti additives. In addition, ZnO:(Cr,Ti) thin films clearly showed the hysteretic behaviors in current-voltage characteristics, and this is due to the suppressed relaxation of trapped charged at the localized electric dipoles in ferroelectric materials. These results indicate that the ZnO:(Cr,Ti) thin films fabricated in this study have multiferroic properties.
G17: Poster Session: Organic II
Session Chairs
Panagiotis Dimitrakis
Sashi Paul
Friday AM, April 09, 2010
Salon Level (Marriott)
9:00 PM - G17.1
Design and Simulation of Molecular, Single-electron Latching Switches.
Nikita Simonian 1 , Andreas Mayr 2 , Konstantin Likharev 1
1 Physics and Astronomy, Stony Brook Univeristy , Stony Brook, New York, United States, 2 Chemistry, Stony Brook University, Stony Brook, New York, United States
Show AbstractLatching switches, i.e. two-terminal electronic devices with resistive bistability, may enable high-density resistive memories and hybrid CMOS/nanoelectronic integrated circuits of unprecedented density – for a recent review, see, e.g., Ref. 1. Despite the recent progress in fabrication of latching switches based on metal oxides and amorphous silicon [1], whose bistability is based on reproducible formation/dissolution of conducting filaments, scaling the hybrid circuits beyond the 10 nm frontier may require such devices based on other physical principles. We have carried out a preliminary design and ab-initio simulation of a single-electron latching switch based on a system of two linear, parallel, electrostatically-coupled molecules: one implementing a single-electron transistor and another a single-electron trap. Both molecules consist of carefully chosen, chemically-synthesizable groups: the benzobisoxazole donor and a naphthalenediimide acceptor playing the role of single-electron islands and alkane chains working (mostly) as tunnel junctions. In order to ensure a sufficient (~10^15) ratio of the retention time to the switching time of the device, the effective island group HOMO level in the trap molecule in its charged state, at switching bias, should be close to the effective valence or conduction band edge of the chain. On the contrary, at the retention bias, the HOMO level has to be close to the middle of the chain band gap. At these conditions, the alkane chain performs the function of an intermediate single-electron island. Similarly, in the charged state of the transistor molecule, the effective HOMO level has to be sufficiently close to the valence or conduction band edge of the chain, to ensure sufficiently high current (~0.1 nA) flowing through the device.To verify the quality of our design, we have carried out transport calculations based on the combination of two techniques: the general theory of single-electron tunneling in systems with discrete energy spectrum [2], which had been extended earlier to molecular systems [3], and the ab-initio calculation of the molecule’s electron structure. The latter part has been done using the Siesta software package, based on the DFT approximation [4], which had been modified to allow an account of image-charge and electrostatic-coupling effects. Our results show that such molecular assemblies of length below 10 nm and a footprint area of the order of 1nm^2 may combine sub-microsecond switching times with multi-year retention times. We have also calculated the effects of the self-assembled-monolayer (SAM) implementation of such switches on their transport properties.[1] K. K. Likharev, J. of Nanoelectron. & Optoelectron. 3, 203 (2008).[2] D. V. Averin, A. N. Korotkov, and K. K. Likharev, Phys. Rev. B 44, 6199 (1991).[3] N. Simonian, J. Li, and K. K. Likharev, Nanotechnology 18, 424006 (2007).[4] See online at http://www.icmab.es/siesta/.
9:00 PM - G17.2
Resistive State Switching in Micron and Sub-micron Size Cu-TCNQ Nanowire Devices.
Arup Raychaudhuri 1 , Phanindra Sai 2
1 , S.N.Bose National Centre for Basic Sciences, Kolkata India, 2 Department of Physics, Indian Institute of Science, Bangalore India
Show AbstractMaterials with reversible switching properties are desirable for future high density non-volatile memory applications. Materials with large difference between ON and OFF states, non destructive read out of the states and low process complexity are preferred. In this paper we report resistive switching in device of the structure Cu(base)/Cu-TCNQ/Metal (top electrode). The switching devices contain Cu-TCNQ nanowires which were grown by thermal evaporation onto a copper film coated glass substrate. We were able to show reversal switching behavior with memory in devices with Pt top electrode in devices approaching micron dimensions (1micron to 10 micron diameter of top electrode).. The top metal electrode in this case made by a focused ion beam (FIB). The devices showed substantial switching at around 2-3V range. The switching ratio (Roff/Ron) can vary by a large amount depending on the metal electrode used and the training. We were able to obtain Roff/Ron ~400 at a small reading voltage of 0.5V.To explore whether switching can be seen in submicron devices we studied switching in devices of submicron size (~40nm). The top electrode in this case is a metallic tip of the conducting probe Atomic Force Microscope (c-AFM). Reproducible memory switching has been seen in such sub-micron structures at voltages ~1V-2V. This observation shows that these switches consisting of nanowires can in principle perform down to size ranges that would allow large packing density.
9:00 PM - G17.3
Characteristics of Organic Memory Using Metal Oxide Nano-clusters.
You-Wei Cheng 1 , Tzu-Yueh Chang 1 2 , Po-Tsung Lee 1 2
1 Display Insititude and Department of Photonic, National Chiao Tung University, Hsinchu Taiwan, 2 Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu Taiwan
Show Abstract In past decades, conjugated organic materials have been widely applied in organic electronic and optoelectronic devices such as organic thin film transistors, organic light emitting diodes, organic photovoltaic cells, etc... One of the candidates for next generation memory devices, organic memory, is emerging because of greater scope for better scalability, low-cost fabrication, mass production capability, and mechanical flexibility. Many published results have paid attention to organic memories with nano-structured materials, for example, an aluminum core covered with an aluminum oxide shell, alkanethiol capping of gold nano-particle, and so on, inside the organic layer as a charge trapping center. In this report, electrical properties of organic memory device with tri-layer structure, MoO3 nano-cluster layer sandwiched between Alq3 thin films, were investigated. Organic memories using this kind of structure exhibited large ON/OFF current ratio about 10000, long retention time over 1hr, and an electrically programmable character. The formation of the bistable resistance switching of the reported structure originated from charge trapping effect of MoO3 nano-clusters layer. Moreover, the current-voltage (I-V) characteristics of the reported device were quite different from those of OBD using MoO3 nano-particles. No negative differential resistance was observed in the I-V curve of the reported device. This may due to the distinct surface morphology of the MoO3 layer on the Alq3 thin film. Besides, the simple structure of the reported device indicates that it can be easily embedded into the well-developed semiconductor fabrication processes.
9:00 PM - G17.4
Resistive Memories Based on Self-organized CVD Cu Nanoparticles on Polythiophene Layers.
Panagiotis Dimitrakis 1 , G. Papadimitropoulos 1 , L. Palilis 1 , M. Vasilopoulou 1 , A. Speliotis 2 , P. Argitis 1 , D. Davazoglou 1 , P. Normand 1
1 Inst. of Microelectronics, NCSR Demokritos, Aghia Paraskevi Greece, 2 Inst. of Materials Science, NCSR Demokritos, Aghia Paraskevi Greece
Show AbstractOrganic memory devices offer an attractive alternative for low-cost ultra-dense data storage. The existence of metal nanoparticles embedded into polymers has been found to increase substantially the functionality of polymeric materials modulating their resistivity values. Actually, these are responsible for the resistivity switching of the polymer matrix between a low and a high-resistance states that constitute the two digital logic states “0” and “1”. In this context, we investigate the self-organization of Cu-NPs on the surface of a regioregular poly(3-hexylthiophene) (RR-P3HT) semiconducting layers on glass substrates. Due to the vertical stacking properties of RR-P3HT chains, S atoms are presented at the surface of the layers. Here, we report on the fabrication of hot-wire chemical vapor deposition (HW-CVD) Cu-NPs embedded in organic materials leading to memory effects. On glass substrates Al strip lines were evaporated through a shadow mask forming the bottom electrodes (BEL) of the device structures. Next, RR-P3HT (~10 mg/ml in chloroform) is spin-coated and annealed at 130 °C for 10 mins, resulting in a ~30-40 nm thick layer. A home-made hot-wire (tungsten) CVD with a vertical type cold wall reactor of stainless steel was used for Cu-NPs deposition from the hexafluoroacetylacetonate(hfac) Cu(I) trimethylvinylsilane(tmvs). The depositions were carried out at a pressure of 2 Torr and substrate temperatures in the range of 100-150 °C for a few minutes. The layer of Cu-NPs is covered by a ~30nm thick layer of PMMA. Al top-electrodes (TEL) were evaporated through a shadow mask having direction perpendicular to the bottom electrodes. The area of each device is 1 mm2. Electrical characterization of the fabricated samples was carried out in terms of current-to-voltage (I-V) measurements and admittance spectroscopy (10Hz-1MHz). For all measurements BEL was grounded and the voltage was applied on the TEL.AFM measurements revealed that the mean size of HW-CVD Cu-NPs is about 3.5nm compared to 6nm NPs formed by PVD. Resistivity switching was observed. At HRS the conduction was found to be due to Poole-Frenkel mechanism while at LRS it was due to SCLC. In addition, some samples exhibited clear negative differential resistance (NDR) regions in the I-V characteristics for both bias polarities. Switching was achieved by applying -8 V /5 s and +6 V/ 5s voltage pulses to obtain the HRS (logic “0” or programming state) and LRS (logic “1” or erase state) respectively. Optimization of surface density of Cu-NPs and TEL and BEL materials are necessary for efficient and stable memory windows.
9:00 PM - G17.5
Hybrid Polymer-quantum Dot Based Single Active Layer Structured Multi-functional Device (Organic Bistable Device, LED and Photovoltaic Cell).
Won Kook Choi 1 , Don-Ik Son 1 , Dong-Hee Park 1
1 Thin Film Material Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of)
Show AbstractWe demonstrate the hybrid polymer-quantum dot based multi-functional device (Organic bistable devices, Light-emitting diode, and Photovoltaic cell) with a single active-layer structure consisting of CdSe/ZnS semiconductor quantum-dots dispersed in a poly N-vinylcarbazole (PVK) and 1,3,5-tirs- (N-phenylbenzimidazol-2-yl) benzene (TPBi) fabricated on indium-tin-oxide (ITO)/glass substrate by using a simple spin coating technique. The multi-functionality of the device as Organic bistable device (OBD), Light Emitting Diode (LED), and Photovoltaic cell can be successfully achieved by adding an electron transport layer (ETL) TPBi to OBD for attaining the functions of LED and Photovoltaic cell in which the lowest unoccupied molecular orbital (LUMO) level of TPBi is positioned at the energy level between the conduction band of CdSe/ZnS and LiF/Al electrode (band-gap engineering). Through transmission electron microscopy (TEM) study, the active layer of the device has a p-i-n structure of a consolidated core-shell structure in which semiconductor nanocrystals are uniformly and isotropically adsorbed on the surface of a p-type polymer core and the n-type small molecular organic materials surround the semiconductor nanocrystals.