Symposium Organizers
Alshakim Nelson IBM Almaden Research Center
Azad Naeemi Georgia Institute of Technology
Hyungjun Kim Yonsei University
Hyun Wook Ro National Institute of Standards and Technology
Dorel Toma TELUS Technology Development Center
F1: Copper Interconnects
Session Chairs
Tuesday PM, April 06, 2010
Room 2010 (Moscone West)
9:45 AM - **F1.1
Recent Advances in Copper Based Interconnect Reliability.
Zsolt Tokei 1 , Kristof Croes 1 , Steven Demuynck 1 , Thomas Kauerauf 1 , Gerald Beyer 1
1 , IMEC, Leuven Belgium
Show AbstractKey aspects of interconnect reliability will be reviewed including copper contact reliability, time dependent dielectric breakdown (TDDB) of low-k dielectrics, stress-induced voiding (SIV) and electromigration (EM) of scaled copper low-k structures. The link between material properties, active physical mechanisms responsible for the degradation and the experimentally observed reliability performance will systematically be highlighted. Copper contacts are being investigated as an alternative contact material to W-based metallization for several years. Although reliability issues associated with scaled copper contacts is an ongoing concern, the appropriate test methods for assessing the reliability margin are less well-defined. We will analyze various diffusion barriers, test structures, methods and provide a benchmark to W-metallization. Another important aspect is low-k dielectric reliability. It has been part of the back-end-of-line reliability research for several years by now. Leakage and breakdown properties are important criteria for selecting low-k materials. Besides the intrinsic properties the damascene process itself introduces several unwanted effects. The TDDB performance is impacted by virtually all fabrication steps as well as the integration method. This is the reason for which the test is well-suited for comparing different integration and process schemes. Examples include the impact of dielectric modification caused by plasma exposure, interface modification induced by chemical mechanical polishing, line edge roughness caused by patterning, spacing variation and thickness variation across the wafer, single vs. double patterning, layout impact, etc. Several aggressively scaled single and dual damascene examples will be shown. For stress induced voiding the choice of test structure and test conditions is of importance when integrating low-k materials. A material independent reliability model describing a wide temperature range (150C-300 C) is proposed. The validity of the model will be supported by numerous experimental evidences and finite element modeling. It is known that the resistivity of interconnects increases with each generation, while at the same time the EM reliability margin is shrinking. A wide range of dimensions will be analyzed along with a projection to sub-30nm dimensions. The low-k results will be benchmarked against an oxide reference. In dual damascene interconnects the choice of metal diffusion barriers is of critical importance as well. The selected examples will include a detailed study of the influence of pre-clean and barrier choice on the EM phenomenon.
10:15 AM - F1.2
Effect of TaN Stoichiometry on Barrier Oxidation and Defect Density in 32nm Cu/Ultra-Low K Interconnects.
Andrew Simon 1 , Frieder Baumann 1 , Tibor Bolom 2 , Jong Guk Park 3 , Craig Child 2 , Ben Kim 4 , Patrick DeHaven 1 , Robert Davis 1 , Oluwafemi Ogunsola 1 , Matthew Angyal 1
1 , IBM Systems and Technology Group, Hopewell Junction, New York, United States, 2 , GLOBALFOUNDRIES Inc, Hopewell Junction, New York, United States, 3 , Samsung Electronics, Hopewell Junction, New York, United States, 4 , STMicroelectronics, Hopewell Junction, New York, United States
Show Abstract A major focus of recent semiconductor interconnect development has been the integration of ultra-low k (ULK) dielectrics with Cu wiring. These ULK materials present particular problems for metals processing due to the porosity needed to achieve dielectrics constants < 2.5. We present the results of a study illustrating the sensitivity of Cu/ULK Dielectric interconnect structures to TaN barrier stoichiometry. The structures studied were 32nm-groundrule dual-damascene 2:1 aspect ratio (AR) lines and 3.5:1 AR vias. The structures were etched in a porous ULK dielectric (k=2.4) and were deposited with TaN/Ta barrier and Cu seed layers using commercially available ionized PVD tooling. In initial studies, the N2 flow was adjusted to give a TaN stoichiometry of ~4:1 Ta:N. Construction analysis of the Cu/ULK line structures was done by TEM. One feature of particular interest in the TEMs was the presence of two distinct bands in the TaN/Ta barrier layer. An inner, darker-colored band is observed closest to the Cu fill metal, with a lighter-colored band with roughened edges visible around the trench periphery. The dark appearance of the inner band is normal, based on previous TEMs of Ta/Cu interconnects, but the lighter tone of the peripheral Ta(N) band is atypical and usually characteristic of oxidation. To assess the stoichiometry of the Ta(N), EDX and EELS line-scans were done which traversed the TEM of trench structure. Plots of oxygen EELS signal overlaid on top of the Ta EDX signal show a significant oxygen presence deep inside the barrier, suggesting oxidation or oxygen permeation through ~30-50% of the barrier layer’s thickness. The full EELS spectra of the oxygen signals confirm a different bonding state for oxygen within the barrier layer vs. oxygen in the dielectric, confirming that the oxygen has reacted with the Ta to oxidize the barrier. The oxidation of the TaN/Ta barrier is unusual in non-porous dielectrics, and is likely due to the porous material’s greater ability to adsorb oxidizing species. Barrier oxidation is of particular concern in preventing dewetting of the Cu from the oxidized Ta(N), or oxidation of the Cu itself. An alternative liner process, with increased N2 flow to give a TaN stoichiometry of ~2.3:1 Ta:N, was tested for comparison. TEMs and EELS/EDX line scans similar to those for the previous samples were overlaid and compared to assess oxidation of the barrier. In contrast to the lower-nitrogen content samples, the oxygen signal stops at the barrier/dielectric interface and no oxidation of the barrier is seen. The higher integrity of the revised barrier is reflected in defect density studies of a 32nm electromigration test structure comparing the two different TaN stoichiometries. The defect density for wafers deposited with the 2.3:1 Ta:N stoichiometry TaN process is ~50% lower than that found for the barrier with the lower nitrogen stoichiometry.
10:30 AM - F1.3
FIB Patterning to Investigate Grain Boundary Scattering in Copper Films.
Boyd Evans 1 , Michael Miller 2 , Tae Hwan Kim 3 , Nagraj Kulkarni 4 , An-Ping Li 3 , Don Nicholson 5 , Edward Kenik 2 , Harry Meyer 2
1 Measurement Science and Systems Engineering, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States, 2 Materials Science and Technology, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States, 3 Center for Nanophase Materials Sciences, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States, 4 Materials Science and Engineering, University of Tennessee, Knoxville, Tennessee, United States, 5 Computer Science and Mathematics, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States
Show AbstractInvestigating the primary contributors to the high resistivity in nanoscale copper interconnects is a topic of active research using the Four-Probe Scanning Tunneling Microscope (STM) technique at ORNL. Preliminary results appear to indicate that grain boundary resistivity contributions can be significant due to the small grain sizes in damascene lines and impurity segregation on grain boundaries that can increase specific grain boundary resistivities. We have been utilizing a subtractive patterning approach based on Focused Ion Beam (FIB) milling of blanket electroplated and high purity or intentionally doped (with Cl, S, C) sputter deposited copper films having large grain sizes (1 micron or higher) in order to measure the specific grain boundary resistivity using the Four-Probe STM. In this presentation, we will discuss techniques for Ga ion beam milling of copper films using an FEI Dual-Beam FIB system in order to obtain serpentine features having varying widths (200-1000 nm) while minimizing the Ga implantation during the milling process. Preliminary 3D Atom Probe studies in FIB-patterned lines to quantify the Cu thin film 3D grain structure and the distribution of dopants within the grain boundary network will be discussed.A portion of this research was conducted at the Oak Ridge National Laboratory's Shared Research Equipment (SHaRE) User Facility which is sponsored by the Scientific User Facilities Division, Office of Basic Energy Sciences, U.S. Department of Energy
10:45 AM - F1.4
First Principles Modeling of Resistance in Copper Film.
Don Nicholson 1 , Xiaoguang Zhang 1
1 , Oak Ridge National Lab, Oak Ridge, Tennessee, United States
Show AbstractThere is considerable debate within the metallization community over the relative importance of grain boundary (GB) and interface scattering in the electrical resistivity of thin films and interconnects. We discuss the calculated specific resistances of several GBs. The resistance varies significantly with GB type, with GB impurity concentration, and with the level of relaxation “disorder” associated with the GB. We will discuss both GB resistance and the conductivity matrix of a copper thin film (111 texture) with atomically rough interfaces with vacuum and with Ta (highly strained 110 texture). The conductivity matrix relates the current density in a plane parallel to the surface at depth, ZI, to the electric field in a plane, ZJ. From the behavior of the conductivity matrix as the ZJ is increased the resistivity of films of various thickness, 1-100nm, can be determined. First principles calculations were performed to relax the GB structure and to compare bulk and GB energy of solution of Ga.This research was sponsored by the Laboratory Directed Research and Development Program of Oak Ridge National Laboratory, managed by UT-Battelle, LLC for the U.S. Department of Energy and by the Division of Materials Sciences and Engineering, Office of Basic Energy Sciences, U.S. Department of Energy.
11:30 AM - **F1.5
Fundamental Investigation of the Correlation Between Passivation Film Integrity and Defectivity During Metal CMP.
Yuzhuo Li 2 , Changxue Wang 1 , Yan Li 1
2 CAE/ND, BASF SE, Ludwigshafen Germany, 1 Chemistry, Clarkson University, Potsdam, New York, United States
Show AbstractKey issues in Chemical Mechanical Polishing (CMP) today include reduction of surface defectivity and enhancement of planarization efficiency. More specifically, the polished surface should be free of defects such as scratches, pits, corrosion spots, and residue particles. It is our experience that a defect-free surface can be most effectively obtained by balancing the chemical and mechanical strengths of the polishing ensemble. A high planarization efficiency can be realized through the controlled formation of a passivating film with balanced thickness and density. In this presentation, we report our recent investigation on the correlation between passivation film integrity and surface defectivity in copper CMP.There have been extensive investigations on the copper passivating film formation under oxidizing conditions. In terms of film structure, the molar ratio of Cu:passivating agent varies widely depending upon the film thickness or depth, preparation procedure, pH, type of oxidizer, and the presence of other complexing agents. It is understood that, depending upon experimental conditions, the dissolution of copper ions out of copper surface is inevitable. Under oxidizing conditions, these ions are likely to be cupric. These copper ions may meet and interact with passivating agent in the solution near the copper surface. The interaction may lead to the formation of nanoparticles. In this study, we examined the possible role of these nanoparticles in the formation of a passivating film and its impact on planarization efficiency and corrosion defects.An extensive collection of knowledge about copper complexation can be found in literature. A complexing agent enhances the static etch rate of copper under oxidizing condition while a passivating agent suppresses the static etch rate under the same condition. The key difference between these two types of complexing agents is their mode of interaction with water and the existing Cu-complex. For a complexing agent such as glycine, the Cu-glycine complex is hydrophilic and water soluble. A passivating agent such as BTA, on other hand, is typically hydrophobic and less water soluble. Even though an individual Cu-BTA complex is water soluble, it tends to attracts extra BTA molecules to form a network which leads to the formation of nanoparticless. Therefore, the formation of nanoparticles in the presence of copper ions is a characteristic of a passivating agent. It is generally difficult to investigate these dynamic processes in an aqueous environment. In this presentation, we shall describe the advantages of dynamic NMR technique to investigate the fate of cupric ions in the presence of various complexing compounds. Furthermore, the influence of abrasive particles on the fate of cupric ions as well as the passivating film integrity will also be described.
12:00 PM - F1.6
Direct Measurement of Grain Boundary Resistivity in Copper Interconnects Using a Four-probe Scanning Tunneling Microscope.
Tae-Hwan Kim 1 , B. Evans 2 , N. Kulkarni 3 , D. Nicholson 4 , X. Zhang 1 , E. Kenik 5 , H. Meyer 5 , An-Ping Li 1
1 Center for Nanophase Materials Sciences, Oak Ridge National Lab, Oak Ridge, Tennessee, United States, 2 Measurement Science & Systems Engineering Division, Oak Ridge National Lab, Oak Ridge, Tennessee, United States, 3 Center for Materials Processing, University of Tennessee, Knoxville, Tennessee, United States, 4 Computational Materials Sciences Division, Oak Ridge National Lab, Oak Ridge, Tennessee, United States, 5 Materials Science and Technology Division, Oak Ridge National Lab, Oak Ridge, Tennessee, United States
Show AbstractCopper is the current choice of the interconnect metal in integrated circuits due to its higher electrical conductivity and improved electromigration reliability in comparison with aluminum. With reducing feature sizes, the resistivity of copper interconnects fabricated using a damascene technology increases dramatically because of electron scattering from surfaces, impurities and grain boundaries (GBs). Continuing dimensional reductions of electronic devices have posed significant challenges to our understanding of the relative importance of various electron scattering mechanisms in nanostructured copper interconnects. The uncertainties arise from the various interpretations of experimental results that rely on the well-known theories of Fuchs-Sondheimer and Mayadas-Shatzkes. In order to gain a better understanding of the contributions of GB in nanostructured copper interconnects, we have made copper lines from poly-crystalline films using focused ion beam milling, and measured resistances inside individual grains and across GBs directly with a four-probe scanning tunneling microscope (STM). Discrete jumps in resistance have been observed when STM probes go across GBs which can be attributed to GB scattering. The specific GB resistivity has been derived. A first-principle calculation of the GB resistance and the role of impurities have been analyzed using a generalized Bloch method. The results provide compelling evidence on the importance of grain boundary scattering process and shed new light to the pathway of reducing the interconnect resistivity. This research at Oak Ridge National Laboratory's Center for Nanophase Materials Sciences and Shared Research Equipment (SHaRE) User Facility was sponsored by the Scientific User Facilities Division, Office of Basic Energy Sciences, U.S. Department of Energy.
12:15 PM - F1.7
Accurate Evaluation of Specific Contact Resistivity of Multi-layered Silicon-based Ohmic Contacts.
Madhu Bhaskaran 1 , Sharath Sriram 1 , Anthony Holland 1
1 Microelectronics and Materials Technology Centre, RMIT University, Melbourne, Victoria, Australia
Show AbstractElectrical contacts to devices which pose low resistance continue to be of interest as the dimensions of devices decrease and nanotechnology demands better means of creating electrical access. In order to study and estimate the resistance of such contacts or the resistance posed by the interface(s) in such contacts, accurate test structures and evaluation techniques need to be used. The resistance posed by an interface is quantified using its specific contact resistivity (SCR), which is denoted using ρc (units: Ωcm2) [1]. Cross Kelvin resistor (CKR) test structures have been used for the measurement of low values of SCR.A simplified approach to this problem of SCR evaluation using the CKR test structures with varying contact sizes is discussed and is shown to be accurate for the estimation of low values (<10-8 Ωcm2) of SCR. This presentation discusses the use of CKR test structures and highlights analytical expressions, using a combination of which a simplified technique to accurately determine SCR was developed [2]. The analytical model described for circular contacts is based on Bessel function expressions. Using several contacts of different diameter (d) with d/w ≤ 0.4 (w is the width of the CKR arms), the parasitic resistance can be accurately accounted for by extrapolation of experimental data to d/w → 0.The accuracy of this technique has been demonstrated using two types of ohmic contacts – aluminium (Al) to titanium silicide (TiSi2) contacts [3] and aluminium to nickel silicide (NiSi) to doped silicon contacts. The SCR of aluminium to titanium silicide (Al-TiSi2) ohmic contacts was evaluated to be as low as 6.0 x 10-10 Ωcm2. Low values of SCR for ohmic contacts incorporating aluminium and nickel silicide for both antimony- and boron-doped samples have been evaluated. The influence of annealing on these SCR values is also reported. SCR values as low as 5.0 x 10-9 Ωcm2 to antimony-doped silicon and 3.5 x 10-9 Ωcm2 to boron-doped silicon were evaluated. These values represent some of the lowest reported for a metal silicide to n-type silicon, while the value of 3.5 x 10-9 Ωcm2 is the lowest value reported for a metal silicide contact to p-type doped silicon. Analytical models were created for the above discussed ohmic contacts and were used to verify the low values of SCR which were measured. Finite element models were created for Al-TiSi2 ohmic contacts and were used to validate the new technique for SCR determination. Preliminary finite element modelling for Al/NiSi/B-doped Si ohmic contacts is also discussed.References:1. D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. Hoboken, NJ: Wiley, 2006, pp. 127-184.2. A. S. Holland, G. K. Reeves, M. Bhaskaran, and S. Sriram, IEEE Trans. Electron Dev. 56 50 (2009)3. M. Bhaskaran, S. Sriram, and A. S. Holland, IEEE Electron Dev. Lett. 29 259 (2008)
12:30 PM - F1.8
Copper Migration During Tungsten via Formation.
Jeff Gambino 1 , Ed Cooney 1 , Will Murphy 1 , Cameron Luce 1 , Steve Mongeon 1 , Ning Lai 1 , Bob Zwonik 1 , Felix Anderson 1 , Laura Schutz 1 , Tom Lee 1 , Tom McDevitt 1
1 , IBM Microelectronics, Essex Junction, Vermont, United States
Show AbstractCopper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects [1]. One challenge with Cu interconnect technology is with packaging, and in particular with wirebonding [2]. Direct wirebonding onto a Cu bond pad is difficult, because Cu oxides easily form in air. Hence, an Al-based terminal wiring layer (Al-Cu) is commonly used in the industry [2-4]. If a fine pitch is required for the terminal wiring layer, then W vias are used to connect the final Al wiring layer to the underlying Cu wiring [4]. Although there have been a few reports on the reliability of W vias landing on Cu interconnects [5,6], there have been no publications on process issues associated with these structures. In this study, we report on a yield problem associated with W via formation on top of Cu interconnects. Copper migration can occur during chemical vapor deposition (CVD) of tungsten, if there are defects in the liner inside the via. Copper can react quickly with SiH4 during the early stages of tungsten deposition, where SiH4-reduction of WF6 is used. Under severe conditions, large amounts of copper diffuse out of the underlying metal layer, resulting in copper silicide formation in the via and leaving voids in the copper wire. This paper will describe the effect of the Cu migration on via yield and microstructure, and will discuss methods to minimize Cu migration. [1] D. Edelstein et al., IEDM Proc., 1997, p. 773; [2] T.A. Tran et al., ECTC Proc., 2000, p. 1674; [3] D. Edelstein et al., IITC Proc., 2004, p. 214; [4] A.K. Stamper et al., AMC Proc. 2004, MRS, 2005, p. 37; [5] A. von Glasow et al., AMC Proc. 2001, MRS, 2002, p. 433; [6]Z. Choi et al., IRPS Proc., 2009, p. 828.
12:45 PM - F1.9
High-yield Adhesion Testing for Ultra-thin Diffusion Barrier and High-k/Metal Gate Films.
Ryan Birringer 1 , Reinhold Dauskardt 1
1 Department of Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractThe integration of new materials at both the interconnect and device levels in CMOS technologies has introduced a range of ultra-thin films and interfaces with largely unknown adhesive and cohesive properties. As film thicknesses decrease and interfaces are engineered to be more robust, quantifying the adhesive and cohesive properties using conventional techniques has become increasingly difficult. In the present study, we propose innovations to the conventional four-point bend adhesion technique and demonstrate their ability to produce quantitative adhesion results with greatly increased test yield for technologically relevant ultra-thin metal diffusion barriers and high-k/metal gate films.In the first example, we consider new Cu metal barrier materials and deposition procedures that are being developed to provide ultra-thin and conformal barrier layers. Barrier layer thickness has become an appreciable fraction of the total interconnect dimensions and must be kept as thin as possible. In addition, since electromigration and stress migration in Cu interconnects are directly related to adhesion and bonding at the metal/barrier interface, robust interfaces with high adhesion values are critical. However, successful quantification of the adhesion of such thin barriers has been difficult given the layer thickness and generally high adhesion values. We demonstrate how the adhesive properties of Cu films and a number of ultra-thin barrier materials, including SiN, SiC, CoWP, and other CVD deposited films, can be quantified using novel modifications of the fracture mechanics-based four-point testing technique. Secondary ion mass and X-ray photoelectron spectroscopy depth profiling is used to quantify interface chemistry, including residual oxygen concentration, and determine how this affects adhesion of the barrier film. In the second example, we consider even thinner films ( <30 Å) at the front-end transistor level. Here new high-k dielectric and metal gate electrode materials are being introduced to address the fundamental scaling limits of SiO2 dielectrics and issues such as poly-silicon gate depletion. We again demonstrate how quantitative adhesion testing can be accomplished with similar techniques and how surface sensitive characterization methods, such as angle-resolved X-ray photoelectron spectroscopy, can be used to characterize interface chemistry. In both examples, adhesion results and significantly improved test yields are compared and contrasted with conventional four-point adhesion metrologies.
F2: Cu Dielectric Interface
Session Chairs
Tuesday PM, April 06, 2010
Room 2010 (Moscone West)
2:30 PM - F2.1
High Quality NH2SAM (Self Assembled Monolayer) Diffusion Barrier for Advanced Copper Interconnects.
Aranzazu Maestre Caro 1 2 , Guido Maes 2 , Gustaaf Borghs 1 , Silvia Armini 1 , Youssef Travaly 1
1 , IMEC, Leuven Belgium, 2 Department of Chemistry, KULeuven, Leuven Belgium
Show AbstractThe trend for future integrated circuits (IC) is decreasing in size beyond the conventional limits. The recent transition from aluminum to copper as the interconnect material for IC is due to copper’s higher resistance to electromigration and its lower resistivity. Unfortunately, copper has high mobility in Si and SiO2 and may cause destruction of electrical connections on the chip. Hence, there is a significant necessity in finding ultra thin, thermally stable, high quality and good adhered diffusion barriers. The most widely used barrier is pure Ta films or layer stacks consisting of Ta and TaN. These have excellent conformality, very good uniformity and high thermal stability. But The continuous scaling down of the interconnect dimensions lead to an essential decrease in the barrier layer effective thickness to less than 5nm; coupled with the replacement of silicon oxide by advanced low-k dielectrics it demand further improvements of the diffusion barrier performance. For that reason Self-assembled monolayers (SAMs), with thicknesses of 2nm or less, have been propose for copper diffusion barrier application. By tailoring the structure of these monomolecular organic films, atomic scale properties can be controlled and selective surfaces and interfaces can be engine as desired for a specific application.In the presented work, the quality of an amino-terminated SAM barrier (NH2SAM) is tested. A high density and the absence of pinholes in the barrier layer are essential for a good barrier performance. First, the macroscopic quality of the NH2SAM barrier has been characterized by Water contact angle (CA) and High resolution AFM (HR-AFM). Secondly, the density and the presence and/or absence of pinholes have been tested by Ellipsometry and Cylic Voltametry (CV). Finally, the intrinsic barrier performance in form of Time- dependent dielectric breakdown (TDDB) lifetime has been extracted from planar capacitor structures that permitted to measure the leakage/Cu diffusion through barrier in the vertical direction.The Contact angle of layers formed at different deposition times show a variation of the hydrophilic SiO2 substrate to hydrophobic already with 1min deposited NH2SAM layer. A 15min deposited NH2SAM (~1nm), results in a continuous and pinhole free layer observed by HR-AFM. The refraction index (η) calculated by ellipsometry, indicates an increase in the density of the layer with the deposition time. On the other hand, cyclic voltametry shows inhibition of the electrochemical reduction of Fe3+ specimen to Fe2+ when NH2SAM is formed on ~2nmSiO2/Si electrodes. A decrease in the capacitive current is observed by increasing the layer thickness and density. The intrinsic barrier performance of the NH2SAM barrier by TDDB is demonstrated with an increase of 10 times the capacitor lifetime by comparing with no barrier system.
2:45 PM - F2.2
Fluoroalkyl Organosilane Nanolayers for Inibiting Copper Diffusion into Silica.
Saurabh Garg 1 , Ranganath Teki 1 , Binay Singh 1 , Michael Lane 2 , Ganpati Ramanath 1
1 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Chemistry, Emory and Henry College, Emory, Virginia, United States
Show AbstractThe downscaling of device feature sizes to the nanometer regime places stringent requirements on the thermochemical integrity of interfaces in device architectures. The copper-dielectric surface is a classic example, where barrier layers are necessary to decrease leakage currents due to copper ionization and diffusion. Currently used 3- to 5-nm-thick metal-based barrier layers are not viable solutions for emerging device technologies because they encroach the space meant for low resistivity copper and thinner layers offer poor conformality in high aspect ratio features. Molecular nanolayers (MNL) comprised of 0.7 to 2 nm long molecules are attractive alternatives since they can immobilize copper through interfacial bonding and form conformal layers by self-assembly. Here, we demonstrate a novel strategy of using low-polarizability hydrophobic organosilanes that inhibit copper diffusion by suppressing Cu ion formation. In particular, we show that incorporating nono-fluoro-trimethoxysilane (NFTMS) at Cu/silica interfaces leads to a four-fold enhancement in barrier properties compared to pristine Cu/SiO2 structures. In addition, we reveal the correlation between interface hydrophobicity and failure time of test devices during biased-temperature-annealing (BTA) by investigating time-dependent defluorination of the fluorocarbon MNL using UV light. X-ray photoelectron spectroscopy (XPS) study shows that, the UV exposure results in fluorine removal by selective cleavage of C-F bond, resulting to a factor of 4 decreases in the fluorine content after 250 min of UV treatment. This result is in agreement with the consistent decrease in the contact angle, indicating decreased hydrophobicity of the interface. Sessile 50 µL DI water drops on the NFTMS-MNL surface exhibit a contact angle of 107° ± 3°, which plunge to 71° ± 4° after texp = 250 min. We observe a factor of ~ 2 decrease in the BTA failure times after 250 min of UV exposure, suggesting the importance of hydrophobic interface resulting from fluorine moieties. The superior barrier properties of the fluoralkyl nanolayer are attributed to diminished water intake which inhibits Cu ion formation due to the higher hydrophobicity of the fluoroalkyl moieties. Our strategy offers promise for realizing dielectrics and interfaces with tunable moisture content, important for enhanced barrier performance.
3:00 PM - F2.3
Fabrication of Organic Thin Films for Copper Barrier Layers Using Molecular Layer Deposition.
Paul Loscutoff 1 , Scott Clendenning 2 , Stacey Bent 1
1 Chemical Engineering, Stanford University, Stanford, California, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractDevice scaling predicts that copper barrier layers of under 3 nm in thickness will soon be needed in back-end processing for integrated circuits, motivating the development of new barrier layer materials. One possible solution under investigation is organic thin films. In this work, nanoscale organic thin films for use as copper barrier layers are deposited by molecular layer deposition (MLD), a technique analogous to atomic layer deposition for inorganic films, utilizing a series of self-limiting reactions of organic molecules. A major advantage of MLD for such barriers is the ability to tailor the properties of the organic barrier by changing the organic small molecule reactants. These changes can be combined to optimize desirable barrier properties, including high film density, high copper surface adhesion, high thermal stability, and low copper diffusion through the film. Three systems are examined as copper diffusion barriers: the reaction of 1,4-phenylene diisocyanate (PDIC) and ethylenediamine (ED) to deposit polyurea films, the reaction of PDIC and 2,2’-thiobis(ethylamine) (TBEA) to deposit polyurea films with a sulfide-modified backbone, and the reaction of 1,4-phenylene diisothiocyanate (PDITC) and ED to deposit polythiourea films, with a modified coupling chemistry. All films are grown on a silicon substrate that has been modified by vapor deposition of 3-aminopropyltriethoxysilane to yield an amine-terminated surface. Following deposition of the MLD films, copper is deposited through sputtering and evaporation. The copper barrier properties of the film are tested through adhesion and annealing tests, including four point bend testing and TEM imaging to examine the level of copper penetration into the films. The promise and challenges of MLD-formed organic barrier layers for copper interconnects will be discussed.
3:15 PM - F2.4
Thermal Conductance Enhancement at a Molecularly-modified Metal-dielectric Interface.
Peter O'Brien 1 , Jianxiun Liu 2 , Ranganath Teki 1 , Pawel Keblinski 1 , Theo Borca-Tasciuc 3 , Masashi Yamaguchi 2 , Ganpati Ramanath 1
1 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States, 3 Mechanical, Aeronautical and Nuclear Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractAlthough thermal phenomena are not directly responsible for the operation of integrated circuits, they are critical for chip reliability, performance, and design. As heat generation is a major limiting factor in the scaling of device speed and density, controlling interfacial heat transport is perhaps the most important design challenge for emerging device technologies. Here, for the first time, we demonstrate the use of a molecular nanolayer (MNL) at a metal/dielectric interface to enhance the interfacial thermal conductance Gi, as measured by the transient pump-probe thermoreflectance technique. The idea of using a soft organic monolayer to increase the thermal conductance between hard materials is completely unexpected, but has wide-ranging implications for nanoscale heat dissipation in emerging nano/micro-electronic devices. A mode-locked Ti:Sapphire laser with a pulse width of ~100 fs is used to heat a metal-dielectric thin film structure, and the thermal decay profile obtained by monitoring the film’s reflectivity (with ps resolution) is used to extract Gi. Our results show that strongly adhered Cu/MNL/silica interfaces exhibit 60% higher thermal conductance compared to unfunctionalized Cu/silica interfaces. We show that Gi is positively correlated with the strength of interfacial bonds, a result that is supported by molecular dynamics simulations of thermal conductance for different bond strengths. Combined with the previously demonstrated ability to tailor interfacial adhesion through MNL functionalization1, this result enables an entirely new method of engineering the thermal properties of interfaces.
1D.D. Gandhi, M. Lane, Y. Zhou, A. Singh, S. Nayak, U. Tisch, M. Eizenberg, and G. Ramanath: Annealing-induced interfacial toughening using a molecular nanolayer. Nature 447, 299 (2007)
3:30 PM - F2.5
Delamination Nanomechanics at a Molecularly-tailored Heterointerface.
Ashutosh Jain 1 , Saurabh Garg 1 , Ranganath Teki 1 , Michael Lane 2 , Ganpati Ramanath 1
1 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Chemistry Department, Emory and Henry College, Emory, Virginia, United States
Show AbstractPartitioning the interface fracture toughness ΓFT into bond-breaking energy γa and plastic energy γp is essential to develop atomistic models of interface fracture, and is of central importance in designing heterointerfaces for applications. However, uncertainties in crack path, fracture surface area, type and number of bonds broken, and whether or not plastic deformation occurs in both materials pose exacting experimental challenges. Thus, current descriptions of interfacial toughness neglect either plasticity (brittle fracture) or adhesion (ductile fracture) contributions towards interfacial toughness, or are based mainly on theoretical models. Here, we experimentally quantify for the first time these contributions to the ΓFT of a model copper-silica interface with a molecularly tailored monolayer. This model system obviates uncertainties in crack path and the type of bonds broken by constraining fracture to a nanoscopically confined plane via exclusive siloxane bond fissure at the interface, and plastic deformation is confined to the copper layer. Since siloxane bridges are susceptible to hydrolysis, varying the water activity awater allows us to measure ΓFT as a function of γa, and separate and express γp in terms of γa. We find that at high awater the fracture toughness comprises of only γa. Decreasing awater increases γa, but the rate of increase of ΓFT increases above a critical value of γa = γ0, due to the onset of copper plasticity. This result provides a direct method to quantify flow stress σy for thin film copper, in excellent agreement with values determined by nanoindentation and theoretical modeling. At low awater the plastic energy γp increases with γa, given by the equation γp = 1.8(γa - γ0), enabling us to isolate contributions of plasticity as well as its dependence on γa. Our experiments with different film thicknesses and temperatures reveal that copper plasticity is a thermally activated process with an activation energy Ea = 0.015 eV/atom corresponding to parallel glide observed in ultrathin copper films under high stress. Our results constitute the first-time experimental determination of plasticity dependence on adhesion and validation of Griffith-Irwin descriptions for hetero-interfaces where neither plasticity nor bond-breaking components can be neglected. Our approach of confining interfacial fracture to occur through fissure of a single type of bonds in a molecular nanolayer is attractive for understanding partitioning fracture energy into bond-breaking and plasticity components in other materials systems.
3:45 PM - F2.6
Effects of Interface Morphology Corrugation on Fracture Toughness of Molecularly Tailored Copper-silica Interfaces.
Ranganath Teki 1 , Saurabh Garg 1 , Vijayashankar Dandapani 1 , Ashutosh Jain 1 , Michael Lane 2 , Ganpati Ramanath 1
1 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Chemistry, Emory and Henry College, Emory, Virginia, United States
Show AbstractThe structural integrity of the metal-dielectric interface plays a crucial role in the reliability and performance of nanoelectronic devices, e.g., it impacts electromigration, residual stresses and overall chip package integration. Interface morphology plays a key role in the above, especially in multilevel wiring architectures that involve high aspect ratio features. For example, plastic deformation in metal lines is known to be sensitive to the feature size and aspect ratio as well as the stiffness of the adjacent dielectric materials. Furthermore, interfacial non-planarity can lead to higher fracture toughness due to mechanical interlocking, increased debonding area, debond kinking and asperity contacts. Here, we demonstrate the role of interface morphology on Cu-silica interfaces tailored with molecular nanolayers (MNL). We have studied the effect of interface corrugation of different widths, aspect ratios, and spacing on the toughness of Cu/SiO2 and Cu/MNL/SiO2 interfaces. We have also studied the efficiency of such corrugations as crack-stop structures, to address the issue of delamination and chip cracking during fabrication or packaging. Si(001) wafers were lithographically patterned with 2.5 to 20 μm-wide lines etched using tetramethyl ammonium hydroxide and thermally oxidized to obtain a conformal 100-nm-thick silica layer over trenches of varying depths. MNLs of 3-mercaptopropyltrimethoxysilane (MPTMS) were self-assembled on the patterns, followed by Cu film deposition. Thin film sandwich structures with crack paths orthogonal and parallel to the trenches were tested by the four-point bend tests. Our results show that orthogonal trenches exhibit a twofold higher interfacial toughness of the planar Cu/silica interface, and MPTMS functionalization further increases the interface toughness by 33% to ~40 J/m2. Further strengthening of the interface through annealing (at > 400 °C) induced siloxane bridging arrests the interfacial cracks and drives the crack into the wafer, showing promise as effective crack-stop structures. Interface fracture chemistry captured by cross-sectional electron microscopy and fracture surface analysis by X-ray photoelectron spectroscopy (XPS) separate the physical and chemical energy dissipation mechanisms at a heterointerface. Our findings help develop a molecular level understanding of fracture mechanics of interfaces with different feature sizes and aspect ratios, and provide insights to design non-planar interfacial features in complex multilevel thin film stacks used in nanodevice applications.
4:00 PM - F2: Interface
BREAK
F3: Advances in Metal Thin-Film Deposition
Session Chairs
Tuesday PM, April 06, 2010
Room 2010 (Moscone West)
4:30 PM - **F3.1
Atomic Layer Deposited-W Nucleation Layer Prepared Using B2H6 and WF6 for Low-resistance CVD-W Bit Line and Gate Processes of Advanced Memory Devices.
Soo-Hyun Kim 1 , Choon-Hwan Kim 2
1 School of Materials Science and Engineering , Yeungnam University, Gyeongsan-si, Gyeongsangbuk-do, Korea (the Republic of), 2 R&D Division, Hynix Semiconductor Inc., Icheon-si Korea (the Republic of)
Show AbstractChemical vapor deposition (CVD) of tungsten (W) is a technology with a long history and has been successfully used for fabricating interconnects of semiconductor devices for last 20 years. But, the technology roadmap for semiconductor devices shows ever-shrinking line width and its thickness as well as contact or via diameter. Eventually, their dimensions start to approach the mean free path for electron scattering of the material used in the interconnect structure, such as ~ 41 nm for W. This leads to the unwanted increase in electrical resistivity due to the proportionately increased electron scattering from the surfaces as its linewidth, thickness, and contact diameter decrease, often described as the “size effect”. Thus, in order to overcome the size effect on the resistivity of W film and realize the excellent speed performance of the circuit, a new process on CVD-W film should be investigated. Generally, CVD-W films are deposited by 2-step process; a deposition of very thin W nucleation layer and a subsequent growth of relatively thick bulk CVD-W film. This gives the possibility that the properties of the CVD-W film, including its resistivity can be controlled and improved by controlling the process of W nucleation layer because the underlying film can have considerable effects on the properties of the metal film growing on it. In this talk, first, I will describe how atomic layer deposited (ALD)-W nucleation layer prepared using a sequential supply of WF6 and B2H6 can reduce the resistivity of CVD-W film growing on it and mitigate the size effect on the resistivity of CVD-W film. And, several issues are addressed for integrating this low-resistivity CVD-W (LRW) film into the memory devices. Finally, I will show the electrical performances of LRW film as a bit line, gate line, and metal contact of memory devices.
5:00 PM - F3.2
Organometallic Chemical Liquid Deposition (OMCLD) of Cu/SiO2 Films for 3D Filling in Microelectronic Applications.
Kilian Piettre 1 2 , Virginie Latour 1 , Olivier Margeat 3 , Vincent Colliere 1 4 , Christine Anceau 2 , Jean Baptiste Quoirin 2 , Bruno Chaudret 1 , Pierre Fau 1 4
1 LCC, CNRS, Toulouse France, 2 , ST microelectronics, Tours France, 3 , Université de la Méditerranée, Marseille France, 4 , Université de Toulouse, Toulouse France
Show AbstractThe actual miniaturization of microelectronics devices leads to increasing practical constraints in the deposition of copper metallic films on complex surfaces likes holes, vias or trenches. The covering or filling of these 3D structures has pushed the development of conformal deposition processes principally based on chemical vapor deposition processes (CVD). In that aim, considerable research work has been done in the field of synthesis of new metal precursor molecules for such deposition systems [1]. Alternatively, liquid methods for metal deposition (electrochemical deposition (ECD) or electroless deposition (EL)) have proven their good conformality even with high aspect ratio trenches. However, such processes can be only carried out on pre-treated surfaces either with electrically conductive layers (for ECD) or sensitized with catalysts for EL [2]. Recently, the role of organometallic chemistry in microelectronics processes has been emphasized [3] and new cost effective copper deposition films have been proposed [4, 5]. In this talk, we present the conformal metallization of silicon structures thanks to a liquid type implementation based on the simultaneous decomposition under H2 reducing gas of a copper precursor ((N,N'-diisopropylacetamidinato) Cuivre (I)) in the presence of a silica source (tetraethoxysilane TEOS). This unique organometallic approach allows the formation of adherent copper/SiO2 clusters around 100 nm thick, on silicon surfaces presenting a large aspect ratio (figure 1). Good coverage of both walls and bottom of the structures can be achieved thanks to the continuous precursor availability in the liquid phase during deposition. The copper precursor decomposition is followed by NMR monitoring and TEOS hydrolysis and condensation reactions are controlled by the precursor chemistry. The reaction pathways involved in the formation of these composite films are detailed and the process parameters are discussed. The resulting films are characterized by scanning electron microscopy (SEM) X-rays diffraction (XRD) and electrical measurements. The resulting Cu/SiO2 films present the double interest of forming an adherent copper layer directly on silica surfaces thanks to SiO2 anchoring, and behave as an effective catalyst layer for a further deposition of thick copper by electroless technique.This approach can easily be extended to other classes of organometallic precursors and brings a new example of the growing role of organometallic chemistry solutions in the field of the actual microelectronic challenges. [1] Zhengwen Li, Sean T. Barry, and Roy G. Gordon, Inorganic Chemistry, 2005,Vol. 44, No. 6[2] Wang Ling Goh, Kee Tchuan Tan, Thin Solid Films 462–463 (2004) 275– 278[3] G. A. Somorjai, F. Tao and J. Y. Park, Top. Catal., 2008, 47, 1[4] C. Barrière, P. Fau et al. J. Mater. Chem., 2008, 18, 3084–3086[5] O. Margeat, C. Barrière, P. Fau, B. Chaudret, 2009, FR2929449_WO2009125143
5:15 PM - F3.3
Application of Ion Scattering Spectroscopy in Combination with Electron Spectroscopy for Ultra Thin Film Stacks of the Sub 32 nm CMOS Technology.
Kornelia Dittmar 1 , Susanne Ohsiek 1 , Hans-Juergen Engelmann 1 , Robert Binder 1 , Martin Trentzsch 1 , Rick Carter 1
1 , Globalfoundries Module One LLC & Co. KG, Dresden Germany
Show AbstractFurther CMOS technology scaling for nodes of 32 nm and beyond requires the successful implementation of new high k gate dielectrics and ultra thin metal gate films in the technology process./1/ Those complicated film stacks are composed of up to 10 films with single thicknesses in the sub A range. The properties of the entire film stack and the inner surfaces are from immense importance for the electrical performance of the transistors. Low Energy Ion scattering spectroscopy (LEIS) is a powerful analysis tool for their characteriza-tion. It is unique in providing the information about the composition of the outermost monolayer of a material. This becomes steadily more important for this ultra thin film, since the common electrons spectroscopy methods integrates typically over the first 1…5 nm nm, which is the overal thickness of the entire metal gate stack. Here in this study applications are presented and discussed. LEIS was applied in combination with common techniques, XPS and AES in order to characterize those metal gate stacks comprehensively. The first example is the investigation of the growth of ALD TaN and Ta films on various ILD materials. Another investigation was carried out on the interaction of work function layers with gate dielectrics. /1/ ECS Transactions 11 (4) 275-283 (2007)
5:30 PM - F3.4
Selective Chemical Vapor Deposition (CVD) of Manganese Self-aligned Adhesion and Barrier Layers for Cu Interconnections in Microelectronics.
Yeung Au 1 , Youbo Lin 1 , Eugene Beh 1 , Yiqun Liu 1 , Roy Gordon 1
1 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Show AbstractIn modern copper (Cu) interconnections in microelectronics, weak adhesion exhibited between the chemical-mechanical polished copper surface and the dielectric capping material can lead to rapid electromigration of Cu and early failure of the wiring. A self-aligned CVD-manganese (Mn) capping process is introduced to strengthen the interface between Cu and dielectric insulators without increasing the resistivity of the Cu. In this CVD process, a vapor mixture of a Mn precursor and molecular hydrogen deposits Mn selectively on copper and not at all on adjacent previously-deactivated surfaces of insulators (either plasma-enhanced (PE) CVD SiO2 or low-k SiCOH). Deactivation of the insulator surfaces is accomplished by exposure to vapors containing reactive alkylsilyl groups. The presence of Mn at the Cu-insulator interface greatly increases the strength of the bonding between the Cu and the insulator. The debonding energy is found to increase approximately linearly with the amount of Mn at the interface, up to values so large that the interface could not be broken apart. This Mn-enhanced binding strength of Cu to insulators is observed for all insulators tested, including PECVD Si3N4, SiCN, SiO2 and low-k SiCOH, as well as thermal SiO2 and atomic-layer-deposited SiO2. This selective CVD Mn capping process should increase the lifetime of advanced copper interconnections. The capacitance delay might also be reduced by substituting a lower-k insulator for the currently-used SiCN, because diffusion of Mn into an insulator also strengthens its barrier properties against diffusion of Cu, O2 and H2O.
5:45 PM - F3.5
The Porogen Structure and Loading Effects on Pore Morphology in Porous Low-k SiCxNy Etch-stop PECVD Films.
Hung-En Tu 1 , Jihperng Leu 1
1 , Department of Materials Science and Engineering National Chiao-Tung University, Hsinchu Taiwan
Show AbstractIn order to meet the requirements of continued reduction of RC delay in the backend interconnects; the semiconductor industry fervently pursues lower keffective, which involves the k-values of interlayer dielectrics (ILDs), etch-stop layer, and their dimensions. While the scaling of ILD down to k<2.5 is impeded by reliability issue and its weak mechanical strength, recent approaches of reducing keffective focus on the aggressive scaling of siliconcarbide-nitride (SiCxNy) as the etch-stop and diffusion barrier in 65nm and 45 nm nodes [1]. To further reduce the dielectric constant of etch-stop layer, porosity are incorporated into SiCxNy films using sacrificial materials as porogen while maintaining fairly good mechanical properties. For example, ultra low k SiCNx/SiCNy bilayer has been plasma-deposited using dimethylsilacyclo -pentane and NH3, followed by UV cure for 32 nm node [2]. In this study, we explore the use of functional group in porogen precursor to control the pore size and porosity in low-k SiCxNy films while maintaining the mechanical strength of etch-stop layer. Particularly, novel 1, 3, 5 -trimethyl-1, 3, 5- trivinylcyclotrisilazane (VSZ) with three vinyl groups was used as the SiCxNy matrix precursor, while polystyrene (PS) and epoxycyclohexane (ECH) were employed as the sacrificial porogen precursors. The porous SiCxNy films were deposited by radio-frequency PECVD under various deposition conditions such as gas ratios, flow rate, pressure, and substrate temperature at 5~20 % porogrn loading, and then the post-annealing treatment was carried out at 400 oC for 1 h. FTIR and XPS spectroscopy were used to characterize the chemical makeup and bonding information of SiCxNy/pogogen hybrid films. Grazing incidence small-angle x-ray scattering analysis (2-D GISAXS) was utilized to quantify the pore size of porous SiCxNy films.VSZ is a good candidate precursor for SiCxNy films because its vinyl group can form a cross-linked structure readily. The pore size of the porous SiCxNy films using PS porogen, which also underwent plasma polymerization, increased from 22 to 35 nm with increasing porogen loading in plasma gas feed. As substrate temperature increased, the pore size also increased due to the higher degree of PS polymerization at higher substrate temperature. In contrast, ECH porogen, which formed the labile fragment (CxHy), but no polymerization under plasma condition, yielded smaller and fixed pore size. In summary, the pore size of SiCxNy films would be controlled by the vinyl functional group according to adjust the porogen precursor flow in plasma gas feed. Key materials properties such as dielectric constant, film stress and mechanical property as function of porosity and porogen chemical structures will be further discussed in the full paper, in addition to pore size and distribution.
F4: Poster Session I
Session Chairs
Hyungjun Kim
Hyun Wook Ro
Tuesday PM, April 06, 2010
Exhibition Hall (Moscone West)
6:00 PM - F4.1
Direct Contact of Al(Ni) Alloys to ITO Layer for TFT-LCDs: Low Contact Resistance and ITO-Al(Ni) Interface Reaction.
Kwanwoo Lee 1 , Dooman Han 1 , Kyunghoon Jeong 1 , Jaegab Lee 1 , Chang-Oh Jeong 2 , Yang Ho Bae 2
1 School of Advanced Materials Engineering, Kookmin University, Seoul, 136-702, Korea (the Republic of), 2 Active Matrix Liquid Crystal Display Division, R&D Team, Samsung Electronics Co., LTD. , Yongin-si, Gyeonggi 449-711, Korea (the Republic of)
Show AbstractDirect deposition of ITO on Al-Ni alloy has been conducted to fabricate barrierless ITO/Al-Ni interconnects for TFT-LCDs. The effects and role of nickel during the sputter-deposition of ITO on a non-equilibrium Al-Ni alloy films and subsequent annealing at 320oC on the growth of interfacial oxide between ITO and Al-Ni alloy and the resulting contact resistance has been examined. Surface oxidation begins with the reaction of Al with the adsorbed oxygen, which produced alumina possibly doped with Ni. The unreacted Ni atoms accumulated in a thin layer immediately beneath the alumina and then rapidly grew into thin layer of Al3Ni, which effectively inhibited Al diffusion. This resulted in the thin oxide and the significant low contact resistance. In addition, at the higher concentration of Ni, the formation of NiO in the alumina tends to increase the thickness of alumina, thus leading to the increased contact resistance. Consequently, the lowest contact resistance was obtained at the concentration in the range of 2.0 at.% Ni. This presentation includes the oxidation process occurring during either sputtering at postannealing steps, and its effects on the specific contact resistance of ITO to Al alloy.
6:00 PM - F4.11
Interfacial Reaction Effect on Electrical Reliability of Au Stud Bump for 3-D Integration.
Young-Bae Park 1 , Myeong-Hyeok Jeong 1 , Jae-Won Kim 1 , Byoung-Joon Kim 2 , Kiwook Lee 3 , Jaedong Kim 3 , Young-Chang Joo 2
1 School of Materials Science and Engineering, Andong National University, Andong Korea (the Republic of), 2 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 3 , Amkor Technology Korea Inc., Seoul Korea (the Republic of)
Show AbstractThrough-Si Via technology has recently been developed in the electronics industry as high performance and miniaturized electronics have become more common. This technology assists in the achievement of high performance and miniaturization because the chip and the substrate are directly connected to solder bumps. The solder bumps become spherical to minimize the surface energy. Bump bridging is caused by the shape of solder in miniaturized electronics. It is limited to applications with a fine pitch. Therefore, a new shape for the bump structure is necessary to address this limitation. Au stud bumps are known to be one of the most promising candidates for the fine pitch interconnection materials because they do not cause bump bridging between adjacent bumps. However, Au stud makes large amount of intermetallic compound with solder at solder joint. Not only excessive intermetallic compound growth but also Kirkendall void formation between Au stud and solder can degrade mechanical reliability. Therefore, it is necessary to understand the intermetallic compound and Kirkendall void growth kinetics. In this work, we performed kinetic studies on the Au stud/Sn bump structure in order to quantify the amount of IMC and Kirkendall void during current stressing.
6:00 PM - F4.12
Inhibitor-enhanced Nucleation Density in Low Temperature CVD.
Shaista Babar 1 , Navneet Kumar 1 , Gregory Girolami 2 , John Abelson 1
1 Materials Science and Engieering, University of Illinois at Urbana Champaign, Urbana, Illinois, United States, 2 Department of Chemistry, University of Illinois at Urbana Champaign, Urbana, Illinois, United States
Show AbstractMicroelectronics fabrication requires the growth of ultra-thin films on dielectric substrates, such as Cu diffusion barriers < 5 nm thick on low-K SiO2 sidewalls. The initial stage of growth is critical: a high nucleation density is necessary to obtain pinhole-free films with rms surface roughness < 1 nm. One approach is to employ surface treatments that enhance the density of active sites on the substrate. Here, we introduce a method based on differential surface kinetics: an inhibitor is added to the CVD process such that the growth rate of initially formed nuclei is greatly reduced compared to the rate at which additional nuclei form, such that uniformly-sized nuclei form everywhere on the substrate. We demonstrate this effect for the growth of the metallic ceramic material HfB2, a high performance Cu diffusion barrier, using the precursor Hf(BH4)4 at 250 C on thermally grown SiO2 substrates. When NH3 is added as a growth inhibitor, the area density of nuclei is enhanced by two orders of magnitude and the rms surface roughness decreases to ~ 0.3 nm. In steady-state growth experiments, in-situ spectroscopic ellipsometry indicates a 20-fold decrease in the HfB2 growth rate in the presence of NH3, and AES, SIMS and XPS reveal a bonded N content < 2 at. %. To explain these data, we propose a site-blocking model in which the inhibitor (i) binds strongly enough to the film growth surface to reduce the net rate of precursor adsorption, but (ii) does not bind as well to the bare substrate surface, such that nucleation can proceed.
6:00 PM - F4.13
Electron Spin Resonance Study of Low-k Dielectrics for Use as Interlayer Dielectrics.
Brad Bittel 1 , Patrick Lenahan 1 , Sean King 2
1 , Penn State University, University Park, Pennsylvania, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractThe electronic properties of low-κ dielectric thin films are important issues in present day ULSI development.[1-6] Leakage currents in general as well as reliability issues such as, time dependent dielectric breakdown (TDDM) and stress induced leakage currents (SILC) are critical problems that are not yet well understood. A topic of current interest is ultraviolet light (UV curing) of low-k materials.[5,6] We have made electron spin resonance (ESR) and current density versus voltage measurements on a moderately extensive set of dielectric/silicon structures involving materials of importance to low-k interlayer systems. Most of the dielectrics studied involve various compositions of SiOC:H. In addition we have also made measurements on other dielectrics including SiO2, SiCN:H and SiN:H. In our study we have made ESR and current density versus voltage measurements both before and after exposing the dielectrics to UV light (hc/λ ≤ 5 eV). We observe extremely gross differences in the ESR spectra and leakage current versus voltage response of these low-k films. We find that UV exposure consistently increases both the density of paramagnetic defects and the leakage current density at a given field. Paramagnetic point defects observed in these films include, E’ centers, silicon dangling bond defects in which the silicon is back bonded to oxygen, possibly carbon dangling bond centers and likely organic radicals. Our preliminary results suggest the UV curing process creates paramagnetic centers which take part in trap assisted tunneling. This tunneling increases dielectric leakage current. Our preliminary results indicate quite clearly that the processing parameters have extremely gross effects upon defect densities within these films. 1.F. Chen et al. Proceedings of the Forty Third International Reliability Physics Symposium, 501 (2008)2.Y. Ou et al. J. Electrochem Soc. 155, (12) G283 (2008)3.J. Michelon and R. J. O.M. Hoofman, IEEE Trans on Dev. and Mcr. Rel. 6, 169 (2006)4.C. Y. Kim, R. Navamathan, H. J. Lee, C.K. Chio, Surlare and Coatings Technology, 202, 5688 (2008)5.S. Eslava, G. Eymery, P. Marsik, F. Iacopi, C. E. Kirschnock, K. Maex, J.A. Martens, and M.R. Baklanov, J. Electrochem Soc. 155, G155 (2008)6.E. Marhrez, N. Rochet, C. Guedj, C. Licitra, G. Imbert, and Y. Lefriec, J. Applied Phys. 100, art. no.124106 (2006)
6:00 PM - F4.14
Ceramic Hard Mask Materials for Use in FEOL and BEOL Patterning Applications.
Vishwanathan Rangarajan 1 , Ananda Banerji 1 , Pramod Subramonium 1 , Hui-Jung Wu 2 , George Antonelli 1
1 PECVD Business Unit, Novellus Systems, Tualatin, Oregon, United States, 2 Customer Integration Center, Novellus Systems, San Jose, California, United States
Show AbstractHard mask layers are becoming more common for critical layers in both front end of line (FEOL) and backend of line (BEOL) patterning schemes. TiN is often used in BEOL low-k applications because of the very high etch selectivity relative to the low-k. However, the weak mechanical properties of the low-k coupled with high compressive stress in the TiN can lead to buckling phenomenon often referred to as line bending. For these reasons, several classes of hard ceramic materials such as SiC, BN, SiBN, and SiBC deposited by plasma enhanced chemical vapor deposition have been developed and studied. We will review the structural, chemical, mechanical, and optical properties of these materials indicating which classes are most likely to meet current industrial needs.
6:00 PM - F4.15
Designing Ultra Low-k Dielectric Materials for Ease of Patterning.
George Antonelli 1 , Gengwei Jiang 1 , Mandyam Sriram 1 , Kaushik Chattopadhyay 2 , Wei Guo 3 , Herbert Sawin 3
1 PECVD Business Unit, Novellus Systems, Tualatin, Oregon, United States, 2 Customer Integration Center, Novellus Systems, San Jose, California, United States, 3 Department of Chemical Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States
Show AbstractOrganosilicate materials with dielectric constant (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the density making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7%C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.
6:00 PM - F4.16
Metal-dielectric Interface Toughening by Ceramization of a Molecular Nanolayer.
Saurabh Garg 1 , Ashutosh Jain 1 , Karthik Chinnathambi 1 , Binay Singh 1 , Vincent Smentkowski 2 , Michael Lane 3 , Ganpati Ramanath 1
1 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Materials Characterization Lab, General Electric Global Research Center, Niskayuna, New York, United States, 3 Chemistry, Emory and Henry College, Emory, Virginia, United States
Show AbstractIntegration of metal-dielectric interfaces using molecular nanolayers (MNLs) is attractive for prospective applications such as laminates in high frequency electronics and packaging, nanodevice wiring and composites. Recent works have shown that annealing-induced siloxane bridging can toughen organosilane-functionalized copper-silica interfaces. While strong bonding of the MNL with the the under- and over-layers is essential for promoting adhesion, the nature of the MNL structure and bonding, especially at temperatures where the MNLs are known to degrade on bare surfaces, are unclear. But tracking atomic-level intermixing and interfacial phase formation in a sub-nm-layer is an exacting challenge due to difficulties in distinguishing Si atoms in the organosilane MNL from Si atoms in the silica substrate, and obtaining sufficient contrast by electron microscopy. Here, we study organogermane-tailored interfaces using a combination of electron spectroscopy and microscopy, and density functional theory calculations to obtain insights into the interface chemical changes. Our results reveal that annealing decomposes the organic monolayer into an inorganic Cu-O-Si network, leading to interface toughening. Our findings indicate that MNL decomposition into inorganic phase at interfaces can be an attractive to approach to tailor the mechanical properties of the interface. We assembled Benzyl-trichlorogermane (BTCG) on silica to form a 0.7-nm-thick nanolayer. Four-point bending fracture tests on as-prepared Cu/BTCG/SiO2 sandwiches revealed a low interface toughness of 2.1 J/m2, comparable to pristine Cu/SiO2 structures. However, interfacial toughness increases monotonically with annealing temperature, yielding values as high as 23.3 J/m2 for Tanneal = 500 °C. Core-level spectra from silica fracture surfaces show a strong Ge signature for Tanneal ≤ 300 °C, that becomes undetectable for Tanneal ≥ 400 °C, suggesting Ge transport and destruction of the organic MNL. This result is corroborated by time-of-flight secondary ion mass spectroscopy profiles showing the smearing of the interfacial Ge spike into the silica layer upon annealing. Incorporation of Ge in the silica weakens the Si-O-Si network, leading to intermixing of Si, O an Cu, forming nanoscale islands of rhombohedral CuSiO3 observable by cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy. Our findings suggest that molecular degradation of the organic MNL to form nanoscopic layer of inorganic metal-oxide-silicon bonds could be an attractive approach for toughening interfaces.
6:00 PM - F4.18
Influence of the Annealing Process of TEOS-SiO2 Substrate on the Formation of Manganese Oxide Layer by Chemical Vapor Deposition.
Nguyen Mai Phuong 1 , Koji Neishi 1 , Seung-Min Chung 1 , Junichi Koike 1
1 Department of Materials Science, Tohoku University, Sendai 980-8579 Japan
Show AbstractThe feature size in advanced ultra large scale integration circuits continuously scales down to achieve high device performance. As the feature size is decreased, resistance-capacitance (RC) delay becomes a major limitation for the device performance. For decreasing the effective resistivity of interconnect lines, the thickness of the barrier layer should be reduced to a minimum possible value. As a possible solution to this issue, we proposed a self formed barrier layer of MnOx using a Cu-Mn alloy by sputtering. We also proposed a chemical vapor deposition (CVD) process for the formation of a thin conformal barrier layer of MnOx.. In the case of CVD, the precursor can react with various elements of a substrate, and the detailed reaction mechanism has not been understood yet. The goal of this paper is to investigate the effects of the silanol group (Si-OH) contained in TEOS substrates on the growth of the MnOx barrier layer.The Mn oxide films were prepared as follows: at first, the 100nm-thick TEOS-SiO2 substrates were annealed in high vacuum for 1h at various temperatures from 150 to 500 oC. Next, Mn oxide films were deposited on the annealed substrates by CVD at 200 oC for 30 min using H2 as a carrier gas and bisethylcyclopentadienyl manganese, (EtCp)2 Mn, as a precursor. The formed film thicknesses were determined from cross-sectional images obtained by transmission electron microscopy (TEM). The water quantities desorbed from the substrates during the annealing process were detected by a thermal desorption spectroscopy (TDS). Chemical bonding states of the CVD-Mn layer was analyzed by x-ray photoelectron spectroscopy (XPS).It was found that amount of the remaining silanol group in the substrates decreases with increasing of the annealing temperature as inferred from the increase of the desorbed water detected by TDS. Thin and uniform Mn oxide layers with amorphous structure were formed on the annealed substrates. The thickness of the Mn oxide film decreased from 8.2 nm down to 1.8 nm with increasing the annealing temperature of the substrates from 150 to 500 oC, respectively. These results suggest an intimate relationship between the thickness of the Mn oxide films and the amount of silanol group in TEOS-SiO2 substrates. Accordingly, the uniform Mn oxide film with an optimum thickness can be obtained by properly annealing the substrate for advanced ultra large scale integration application.
6:00 PM - F4.19
Analysis of Dielectric Constant of a Self-forming Barrier Layer With Cu-Mn Alloys on Low-k Substrates.
Seung-Min Chung 1 , Jun-ichi Kioke 1
1 Material science, Tohoku University, Sendai Japan
Show AbstractAs the device size shirks, Cu/low-k interconnects have been always challenged with search for new barrier/adhesion materials. Recently, the self-forming process of a barrier layer has been successfully demonstrated in a dual-damascene structure by using a Cu-Mn alloy as a seed layer. Since dielectric constant is a very important parameter for device performance in terms of RC delay, we reported the dielectric constant of the self-forming barrier layer on TEOS-SiO2 using a metal-oxide-semiconductor (MOS) structure. However, the dielectric constant of the self-forming barrier on SiOC low-k materials has not been reported yet. In the present work, we investigated the dielectric constant of the self-forming barrier layer on SiOC with a Cu-Mn alloy overlayer.Substrates were dence SiOC films on p-type Si wafers, provided by TOSHIBA. Al-1at.%Si electrodes were sputter deposited to a thickness of 100 nm by using shadow mask in order to measure the dielectric constant of the dense SiOC films. Cu-4at.%Mn alloy was also sputter deposited to 260 nm, followed by metal patterning that was fabricated through a photolithographic process and wet chemical etching to a size of 120 µm x 60 µm. The obtained samples were annealed at 400oC for 30 min under high vacuum condition to self-form a barrier layer. The annealed samples were observed in cross section with a transmission electron microscope (TEM). Diffusion barrier property was examined by measuring concentration distribution with an energy dispersive x-ray spectroscopy (EDS). The dielectric constant was determined by capacitance-voltage (C-V) measurements at 1 MHz. The average accumulation capacitance of SiOC with the Al-Si electrode of 7764±28 µm2 in area was (5.09±0.03) x 10-12 F at -3 V after annealing. The thickness of SiOC dielectric was 38.2±0.6 nm by measuring with cross sectional TEM. These values yielded the dielectric constant of SiOC of 2.83±0.01. Meanwhile, the average accumulation capacitance of SiOC /MnOx barrier layer was (5.37±0.22) x 10-12 F at -3 V and 1 MHz after annealing with the Cu-Mn electrode of 7578±157 µm2 in area. The EDS spectra taken from the interface layer showed an evident peak of Mn, indicating the formation of a barrier layer containing Mn. The thickness of the self-forming barrier layer was 1.6±0.2 nm by using cross sectional TEM. Finally, the dielectric constant of the barrier layer was calculated to be 2.78±0.12. These results indicate that the presence of the thin barrier layer is compatible for advanced low-k interconnect structure.
6:00 PM - F4.2
Influence of Cu and Cu Alloy Electrodes on the Electrical Properties and the Microstructures of the Amorphous In-Ga-Zn-O Thin Film Transistor.
Jung-Ryoul Yim 1 , Sung-Yup Jung 1 , Han-Wool Yeon 1 , Young-Chang Joo 1
1 , Department of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractAmorphous oxide semiconductors as the channel layer of the thin film transistor (TFT) have recently attracted much attention. Among them, an amorphous indium gallium zinc oxide (a-IGZO) has been intensively studied due to its high mobility and excellent subthreshold gate swing even in the amorphous phase. a-IGZO TFTs using indium tin oxides for source/drains electrodes have been focused on. However, much attention needs to be given to metal electrodes for large area application in viewpoint of resistivity. Cu interconnect is used for advanced microelectronic devices because of its low resistivity and high electromigration reliability. However, there are reliability issues, such as Cu oxidation, Cu diffusion into oxides, and poor interfacial adhesion to oxides. Thus, electrode-semiconductor interfacial barriers are required to inhibit Cu oxidation and Cu diffusion into oxides and to improve interfacial adhesion. In addition, the barrier layer needs to be thin to prevent the effective resistance of the interconnect from rapidly increasing as they are increasingly miniaturized to achieve higher performance. Thus, alloying elements to Cu has been suggested because a self-forming diffusion barrier can inhibit Cu diffusion into a-IGZO and the oxidation of Cu alloy electrodes. The barrier layer can also enhance the adhesion between the electrode and the a-IGZO channel layer. We studied the effect of alloying Mg and Mn to Cu on the electrical properties and the microstructures of the a-IGZO TFTs. The resistivity of Cu interconnect, the threshold voltage and the on-off ratio of TFTs were measured to study the electrical properties. The semiconductor-metal interfaces were also analyzed using transmission electron microscopy and electron energy-loss spectroscopy. For this research, bottom gate TFTs were prepared. 100 nm thick SiO2 gate insulators were grown on heavily n-doped Si wafers used as a gate and 50 nm thick a-IGZO channel layers were RF sputtered. Pure metal (Mo and Cu) and metal alloy (2 at.% Mg-Cu , and 2 at.% Mn-Cu) electrodes were deposited by DC sputtering. The TFTs were annealed at 300 °C for one hour in air atmosphere. Mo electrodes TFTs could be turned on after the annealing. On the other hands, Cu electrodes TFTs could not be turned on after the annealing. These resulted from the fact that Mo is stable during annealing while Cu oxidizes and diffuses into a-IGZO easily. The TFTs with Cu(Mg) and Cu(Mn) electrodes could be turned on after the annealing because the self-formed interfacial layer formed between a-IGZO and the electrodes and prohibited the Cu and oxygen diffusion between a-IGZO to Cu alloy electrodes. The thickness of the interfacial product is only a few nanometers and the resistivity of the Cu(Mg) and Cu(Mn) film is below 3 µΩcm. These results can indicate that alloying Mg and Mn to Cu is efficient to enhance the electrical properties and the reliability in a-IGZO TFTs.
6:00 PM - F4.20
Nanocrystalline Diamond Thin Films for Advanced Packaging Applications.
Nirmal Govindaraju 1 , Peter Kosel 2 , Raj Singh 1
1 Department of Chemical and Materials Engineering, University of Cincinnati, Cincinnati, Ohio, United States, 2 Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, Ohio, United States
Show AbstractThe International Technology Roadmap for Semiconductors (ITRS) [1,2] has identified thermal management in packaging applications as one of the “Difficult Challenges” facing the microelectronics industry today. The roadmap projects that by the year 2014 the heat dissipation requirements will be as high as 205 W/cm2 for high-performance microprocessors. Thermal management is also critical in the wide variety of packaging technologies used in optoelectronics, radio-frequency and millimeter wave devices, automotive electronics and solar cells. The advent of advanced packaging technologies such as the System-in-Package (SiP) which incorporate 3D interconnects require the development of new materials and strategies for effective heat removal. One of the critical parameters which significantly affects the efficacy of a given thermal management technology in packaging applications is the thermal resistance of the Thermal Interface Material (TIM). Traditional TIMs have low thermal conductivity values of the order of 0.05 W/cmK [3] while the newly developed solder thermal interface materials have values up to 0.87 W/cmK [4]. However, the latter values are still low, and current TIMs severely restrict heat flow even when high thermal conductivity heat sinks and heat spreaders are used. Another area of significant concern is the occurrence of “hot spots” in single chip and multi-chip 3D packaging applications where this phenomenon severely limits the packing densities. Diamond thin films are excellent conductors of heat due the high Debye temperature of the diamond lattice. Nanocrystalline diamond (NCD) thin films have the added advantage of exhibiting very smooth surfaces as a result of their small grain size. The reduced surface roughness of NCD thin films along with their high thermal conductivity, as compared to state-of-the-art TIMs, makes them attractive for use as low thermal resistance TIMs. This article discusses the development of a process technology which enables the deposition of NCD films over devices fabricated on Si and SiC substrates. Electrical characterization of the devices before and after NCD deposition is presented to demonstrate the viability of the process. Electrical characteristics of devices with NCD deposited on the device side and on the substrate side are presented in order to elucidate the effectiveness of these films in eliminating “hot spots” and for TIM applications. Scanning electron microscopy images and Raman spectra are used to demonstrate the quality of the NCD films. Thermal modeling of NCD films used as TIMs in packaging applications is also presented to demonstrate the advantages of these films in heat dissipation applications. References:1. http://www.itrs.net/Links/2008ITRS/Home2008.htm (2008Tables_FOCUS_B.xls)2. http://www.itrs.net/reports.html (2007 Edition)3. http://www.electronics-cooling.com/articles/1996/sep/sep96_01.php4. M.P.Renavikar et. al.,Intel Technology Journal, 12 (1),1-15 (2008)
6:00 PM - F4.21
Low Temperature Bonding via Copper Nanowires for 3D Integrated Circuits.
Shu Rong Chun 1 2 , Wardhana Sasangka 1 3 , Chee Lip Gan 1 3 , Hui Cai 1 , Chee Mang Ng 2
1 School of Materials Science and Engineering, Nanyang Technological University, Singapore Singapore, 2 , Chartered Semiconductor Manufacturing Ltd., Singapore Singapore, 3 Advanced Materials for Micro- and Nano-Systems, Singapore-MIT Alliance, Singapore Singapore
Show Abstract Three-dimensional (3D) integration is known to be a promising solution to scaling issues in CMOS circuits. It enables improvements in integrated circuits (ICs) performance, power consumption, system functionality and form factor. Wafer or chip bonding is an enabling technology for fabrication of 3D ICs and low temperature bonding is desired for compatibility with back-end-of-line processing conditions in order not to affect the device performance. Hence, it is necessary to research on ways to bring down the bonding temperature effectively. It has been well understood that the melting point of material decreases as the surface to volume ratio increases. This characteristic can be applied to lower down the bonding temperature by changing the copper film with copper nanowires. In this project, a comparison is being done on Film-to-Film, Film-to-Nanowires and Nanowires-to-Nanowires bonding in terms of microstructure and shear strength to demonstrate the above idea. Copper nanowires are fabricated via electrodeposition through nanoporous Anodized Aluminum Oxide (AAO) templates while copper film is achieved by electrodeposition. The bonding technique used is thermocompression Cu-to-Cu bonding. Bonding pressure is fixed at 6.5 MPa, while the bonding temperature is varied from 200 to 350 degree celsius with a duration of 1 hour. In addition, the effect of post annealing is also investigated. Cross-section images captured by using Focused Ion Beam (FIB) revealed good interface between Nanowires-to-Nanowires bonding which is comparable to Film-to-Film bonding. Scanning Electron Microscope (SEM) images of samples after shear test also demonstrated that there is good adhesion between the bonding. In addition, results from shear tests showed an increase in shear strength of Nanowires-to-Nanowires bonding as compared to that of Film-to-Film bonding. With the analysis from both microstructure and shear strength, it is clearly demonstrated that bonding using copper nanowires can lower the bonding temperature effectively with higher shear strength as compared to copper film. In this study, it has been shown that copper nanowires fabricated via electrodeposition through porous AAO template can be used as a bonding intermediate layer. Results have demonstrated that nanowires can lower the bonding temperature effectively as compared to that of the film.
6:00 PM - F4.3
Copper-sulfide Passivation Capping for Cu Interconnects.
Uri Cohen 1
1 , UC Consulting, Palo Alto, California, United States
Show AbstractCopper-sulfide is proposed as a highly selective self-aligned passivation capping film on Cu lines, to improve immunity against electromigration. Copper-sulfide is tenacious, having excellent adhesion (chemically bonded) to the underlying copper lines and strong adhesion to the overlying dielectric capping barrier. Contrary to other passivation schemes, Cu sulfidation is 100% selective. A very thin copper-sulfide film (of about 25-100Å) will be required, and no significant increase of RC delay is expected. Copper sulfidation can be done by a wet or a dry process. Wet sulfidation can be performed as part of (and immediately after) the CMP process, and dry sulfidation can be done prior to, and as part of the plasma enhanced CVD (PECVD) dielectric barrier deposition. While wet sulfidation may be simpler and more economical, it may also have several drawbacks: (a) formation of copper-oxide(s) on the CuXS (1.0 ≤ X ≤ 2.0) film, when exposed to the atmosphere; and (b) formation of thermally unstable phases and/or composition. In contrast, dry sulfidation process is expected to have the following advantages: (a) no oxidation of the CuXS film by exposure to the atmosphere; (b) more versatile control of the CuXS composition and phase(s); (c) plasma activation of the precursor (H2S or S) produces very high gas temperature at the substrate surface, thereby facilitating the formation of the most thermally stable phase (melting point of Cu2S is ~1,130°C); (d) PECVD also facilitates the formation of a very thin (25-100Å) sulfide film with smooth and flat Cu/CuXS interface; and (e) the same PECVD chamber used for the deposition of the dielectric capping barrier can be used for the sulfidation prior to deposition of the capping dielectric barrier.
6:00 PM - F4.4
Formation of Nanocontact Between Nanowire and Metal by Noble Nanoscale Soldering.
Jihye Lee 1 , Joon Kim 2 , Chang-Soo Han 2 , Jeunghee Park 3
1 Department of Nano Manufacturing Technology, Korea Institute of Machinery and Materials, Daejeon Korea (the Republic of), 2 Department of Nano-Mechanics, Korea Institute of Machinery and Materials, Daejeon Korea (the Republic of), 3 Chemistry, Korea University, Jochiwon Korea (the Republic of)
Show AbstractRecently there have been efforts to develop bottom-up fabrication of one-dimensional (1-D) nanostructures such as semiconductor nanowires and carbon nanotubes and to apply them to field effect transistors, light emitting devices, bio-sensors and flexible devices. In order to make advances in industrialization of these 1-D nanostructures-based devices, contacts of 1-D nanostructures needs to be improved for their large-scale, residue-free, and low temperature integration. In this paper, we demonstrate formation of nanocontact by soldering nanowires to metal using solder metals. The contact formation between nanowire and metal was analyzed depending on process variables. Field effect transistor fabricated by using nanoscale soldering showed enhanced electrical characteristics due to improved ohmic contact by nanoscale soldering. This approach provides a large area integration of nanowires at relatively low temperature compared to thermal annealing and can be applied to flexible devices with enhanced reliability.
6:00 PM - F4.5
Evaluation of Sub-micron Scale Local Strength in the LSI Interconnect Structures.
Shoji Kamiya 1 4 , Hisashi Sato 1 4 , Masahiro Nishida 1 4 , Chen Chuantong 1 , Tomoji Nakamura 2 4 , Takashi Suzuki 2 4 , Takeshi Nokuo 3 4 , Tadahiro Nagasawa 3 4
1 , Nagoya Institute of Technology, Nagoya, Aichi, Japan, 4 , JST CREST, Chiyoda-ku, Tokyo, Japan, 2 , Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan, 3 , JEOL, Akishima, Tokyo, Japan
Show AbstractIn this presentation, a new technique leading toward the evaluation of sub-micron scale local strength in the LSI interconnect structures is proposed. It is correlated to the newly launched project to develop the platform for the study of microscopic strength distribution in LSI structures in order to establish a systematic design scheme from the view point of mechanical engineering.Mechanical fracture of small scale structures in LSIs has become a serious issue, especially since low-k materials were introduced to compose sub-micron scale interconnects. Interface toughness of low-k materials was widely evaluated with mm-scale blanket film specimens by using four point bending technique. In order to design the reliability from the view point of mechanical engineering, however, local strength of structures in sub-micron scale where the fracture initiates should be evaluated because the interface of patterned structures may have different strength from that of blanket films.We have recently developed a new technique for the evaluation of interface strength [1]. This technique uses micron-scale small film blocks cut out of the stacking structure as specimens subjected to fracture test. Interface bonding energy is evaluated through the simulation of crack extension in the specimen to take the effect of specimen size into account and also to separate the energy dissipated by plastic deformation. Therefore the evaluation result is in principle independent of specimens used for the experiment. By applying this technique to the interface between a cap layer and Cu film, the experiment performed under an optical microscope with 10 × 10 μm specimen already yielded the interface bonding energy which agrees with the results obtained by the conventional four point bending technique [2].In order to realize the evaluation in the scale of LSI interconnect structures, i.e., smaller than 1 μm, it is necessary to fabricate specimens of this scale at specified places in the structures and to perform the experiment of this resolution with the expected fracture load less than 1μN. For this purpose, new equipment is being developed where SEM/FIB is combined with EBSD and nano-indenter. FIB, EBSD and nano-indenter are used for specimen fabrication, local stress evaluation, and fracture test as well as measurement of local elastic-plastic properties necessary for the simulation, respectively, all performed under SEM observation. These information provide not only a map of local strength distribution but also a possibility toward a systematic design scheme on the basis of mechanical engineering brought into LSI interconnect structures. The aim and outline of the project are reported in the presentation together with the up to date results so far obtained.[1] Thin Solid Films, Vol. 469-470 (2004), p. 248.[2] Mater. Res. Soc. Symp. Proc., Vol. 990 (2007), p. 213.
6:00 PM - F4.6
Thermoreflectance Imaging of Gold Thin Film Wires and Carbon Nanostructures.
Christopher Cardenas 1 , Christopher Knowles 1 , Patrick Wilhite 1 , Francisco Madriz 1 , Michael Rosshirt 1 , Drazen Fabris 1 , Cary Yang 1
1 Center for Nanostructures, Santa Clara University, Santa Clara, California, United States
Show AbstractGaining a better understanding of the thermal transport and heat dissipation of nanoscale structures requires a precise knowledge of the temperature distribution within these structures. Non-contact reflectance based thermal imaging allows for submicron resolution of active microscale structures aiding in the design of future interconnects. The thermoreflectance method yields fast thermal response and sub-microscale spatial resolution using visible light. This work develops a high resolution and high sensitivity thermal vision system consisting of a phase-locked 16-bit CCD and optical microscope. Narrow bandwidth LEDs are used to illuminate 90 nm thick and 1 micron wide thin film gold wires. Wavelengths tested are centered about 470 nm and 530 nm which maximize the change in normal reflectance. The acquired change in normal relative reflectivity of the thin film is then calibrated under uniform heating with a 13 micron thermocouple located at the surface of the film. The resistive heating of the gold thin film under electrical loading is observed and compared to a model that predicts conduction heat transfer to the substrate. Maximum predicted differential temperature increase is 115°C from ambient under electrical loads tested. Using a 1D thermal transport model [1] accounting for thermal diffusion through the film, dissipation to the Si02 substrate, resistive generation within the thin film, and conduction heat transfer to the electrode regions of the structure, the calibrated experimental response is used to characterize the gold/substrate contact resistance and compared with measurements using laser pulse heating. The same approach is employed to determine the temperature distribution along the length of carbon nanofibers with diameters ranging from 100 to 200 nm, and the results are compared with those predicted by the transport model [1].[1] T. Yamada, T. Saito, D. Fabris, and C.Y. Yang, “Electrothermal Analysis of Breakdown in Carbon Nanofiber Interconnects,” IEEE Electron Device Letters 30, 469-471 (2009).
6:00 PM - F4.7
Vacuum-assisted Aerosol Deposition of a Low-dielectric-constant Periodic Mesoporous Organosilica Film.
Wendong Wang 1 2 , Daniel Grozea 2 , Douglas Perovic 2 , Geoffrey Ozin 1
1 Chemistry, University of Toronto, Toronto, Ontario, Canada, 2 Materials Science and Engineering, University of Toronto, Toronto, Ontario, Canada
Show AbstractLow-dielectric-constant periodic mesoporous organosilica thin films are fabricated by vacuum-assisted aerosol deposition, a vapor-phase delivery technique favored by the semiconductor industry. This aerosol deposition strategy for making mesostructured thin films combines the advantages of vapor phase delivery and evaporation induced self-assembly, and at the same time circumvents the difficulty of vaporizing low volatility templates. Vacuum is used to assist both the evaporation of the solvent and the self-assembly of meso-structures inside the aerosol droplets, and the whole process is conducted at room temperature. The dielectric and mechanical properties of these films can be tuned to have a dielectric constant less than 2 and Young's modulus higher than 4GPa, a combination of properties that satiate the immediate need of semiconductor industry.
6:00 PM - F4.8
Fabrication of Transparent InGaZnO Thin Film Transistors with Al2O3 Dielectrics Deposited by Atomic Layer Deposition.
Chang Ho Woo 1 , Young Yi Kim 1 , Hyung Koun Cho 1
1 School of Advanced Materials Science & Engineering, Sungkyunkwan University, Suwon, Gyeonggi-do, Korea (the Republic of)
Show AbstractRecently, thin-film-transistors (TFTs) fabricated at low temperature have attracted a lot of attentions in various applications such as sensors, solar cells, display backplanes, and memory devices. Transparent or flexible TFTs required the high quality channel layers with high mobility and large-area uniformity on glass or plastic substrates [1]. During past ten years, amorphous Si based transistors exposed many problems including high processing temperature, non-stability, and low mobility. Thus, amorphous oxides such as InGaZnO and InZnO as a novel material are proposed. These amorphous oxide TFTs showed relatively high mobility and large-area uniformity, even though low growth temperature. The nominal gate dielectrics such as SiNx and SiOx grown by chemical vapor deposition required thermal energy at appropriate temperature to obtain dense films. The best choice for the deposition of gate dielectrics on flexible substrates is considered to be high-k oxides grown at low temperature by sputtering and atomic layer deposition (ALD). The well-known high-k materials are HfO2 and Al2O3, which have a low leakage current and at least equivalent capacitance thickness. This study investigated the effect of growth temperatures of ALD grown Al2O3 layers on the TFT device performance. The ALD deposition resulted in high conformal and defect-free dielectric layers at relatively low temperature, compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : HNO3 = 3:1, Al2O3 layers were deposited by ALD at various temperatures or lift-off process. Amorphous InGaZnO channel layers were grown by RF magnetron sputtering at a working pressure of 3 mTorr with O2/Ar (1/29 sccm) flow. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayers. The TFT devices were heat-treated in a furnace at nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B) and LCR meter.References[1] M. Nakata, K. Takechi, T. Eguchi, E. Tokumotsu, H. Yamguchi, S. Kaneko, Jpn. J. Appl. Phys 48, 081608 (2009)[2] X. H. Zhang, B. Domercq, X. Wang, S. Yoo, T.Kondo, Z. L. Wang, B. Kippelen, Organic Electronics 8, 718-726 (2007)
6:00 PM - F4.9
Plasma-assisted Contact Shrink for RRAM Application.
Alexey Milenin 1 , Judit Lisoni 1 , Nico Jossart 1 , Malgorzata Jurczak 1 , Herbert Struyf 1 , Werner Boullart 1
1 EtchBEOL, IMEC, Leuven Belgium
Show AbstractWe investigated the patterning of contact features by means of plasma-assisted critical dimension (CD) shrink followed by contact etch to reduce dimensions from 90-nm to 50-nm (moderate shrink) or to sub-30-nm (extreme shrink). Of developing techniques allowing sub-30-nm patterning for contacts, e.g. EUV, nano-imprint, and negative tone development litho, the shrink in plasma reactor is the only one that does not necessarily require new mask sets and can be tested directly with the relaxed pitch litho masks currently existing for 65-nm node. We used 300-mm substrates with 90-nm contacts printed with 193-nm immersion litho on the following stack: 200-nm Resist/60-nm ARC160 Barc/20-nm SiO2/45-nm Si3N4/at least 20-nm of Ni. Such shallow contact etch stopping on Ni was shown to be sensitive to Ni sputtering if a standard high power plasma etch recipe often used in CMOS patterning was applied. Thus, we addressed both aspects of patterning, i.e., shrink and etch.The shrink and etch were performed in an advanced capacitively coupled plasma (CCP) reactor equipped with 2, 27, and 60-MHz generators as well as with two independent gas lines and the capability to fast-switch between them. We achieved well defined contacts having CD of 50-nm using the moderate shrink utilizing 7 cycles of C2H4-based polymer deposition and CF4-based etch, together with a new low-sputter-yield contact etch recipe based on CF4/H2/Ar gas chemistry and utilizing both 27 and 60-MHz power generators. The extreme shrink to sub-30-nm CD required extra attention to the deposited polymer stability to avoid blistering. Finally, imposing limitations on polymer deposition regime, the plasma-assisted contact shrink to sub-30-nm and patterning down to metal were successfully demonstrated for the RRAM application stack. The achieved value of 3σ ≈ 6.4 nm in across-wafer CD uniformity is close to initial ~5.5-nm after litho that allows using such approach as a robust test vehicle for the small contact features evaluation.
Symposium Organizers
Alshakim Nelson IBM Almaden Research Center
Azad Naeemi Georgia Institute of Technology
Hyungjun Kim Yonsei University
Hyun Wook Ro National Institute of Standards and Technology
Dorel Toma TELUS Technology Development Center
F5: Low-<i>k</i> Materials
Session Chairs
David Graves
Hyun Wook Ro
Wednesday AM, April 07, 2010
Room 2010 (Moscone West)
9:30 AM - **F5.1
Mechanisms of Plasma Damage to Ultra-low K SiCOH Dielectrics.
David Graves 1
1 Chemial Engineering, UC Berkeley, Berkeley, California, United States
Show AbstractPlasma etch, strip and clean processes are known to cause damage to ultra-low k dielectric films in interconnect structures. In this talk, I will focus on SiCOH materials. The mechanisms of this damage have been difficult to determine unambiguously in part because of the complexity of the plasma environment. In this talk, I will report our recent progress in using experiments conducted in a vacuum beam apparatus, in which separate, controllable beams of ions, photons, radicals and electrons can be directed to a sample surface under high vacuum conditions. Post-exposure analysis via FTIR is used to characterize changes in bond structure and the extent of damage.The vacuum beam exposures show that damage in O2-containing plasmas can be attributed to some combination of O radicals and the synergistic effects of vacuum ultraviolet (VUV) photons and O2 molecules. O atoms damage the material by diffusing into the pores and abstracting methyl groups, resulting in SiOH bonds. Exposure to atmospheric water vapor appears to play an important role in post-exposure damage generation. But in addition to the role of O atoms, we have discovered in a set of complementary experiments that VUV photons (147 nm) coupled with O2 exposure also generates substantial damage with no O radical present. In both cases, prior exposure of the porous film to rare gas ion impact at ~ 500 eV reduces subsequent damage when the film is exposed to VUV/O2 or O atoms. Finally, I will discuss results of exposing the same materials to a well-characterized inductively coupled plasma in Ar and Ar/O2 mixtures. The combination of vacuum beam and plasma experiments allows a much deeper understanding of mechanisms involved with plasma treatments.
10:00 AM - F5.2
Mechanical Behavior of Hydrogenated Amorphous Silicon Carbide Dielectrics.
Yusuke Matsuda 1 , Sean King 2 , Jeff Bielefeld 2 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractHydrogenated amorphous silicon carbide (a-SiC:H) are attractive materials as etch stop and dielectric layers due to their widely tunable dielectric constants. In the present study we report on the mechanical and fracture behavior of a wide range of a-SiC:H films prepared using PECVD. The dielectric constant was varied from 2.8 to 7.2 and the Young’s modulus from 5 to 207 GPa. The cohesive fracture energy of the films was found to increase with elastic modulus and exhibited a transition from cohesive to adhesive failure at a modulus of ~ 60 GPa. Some non-stoichiometric compositions were found to exhibit surprisingly high fracture energy that was rationalized in terms of the onset of limited plastic deformation. Most importantly, we examined the sensitivity of the films to moisture assisted cracking which is a ubiquitous phenomenon in organosilicate glass dielectrics. We found no evidence of moisture assisted cracking even in test environments that ranged from extremely dry nitrogen to those containing 90% relative humidity. A model is presented to describe the resulting crack velocity behavior in terms of a thermally activated kinetic bond rupture process with a measured Si-C bond rupture activation energy of ~ 288 kJ/mol. The moisture insensitivity is due to the lack of Si-O bonds, which are well known to react with water molecules, thus leading to moisture assisted cracking. Finally, oxygen was incorporated into one of the a-SiC:H films to investigate the effects of increasing Si-O bonds incorporation on fracture energy and moisture assisted cracking. The implications for the use of a-SiC:H as dielectric layers are discussed together with the potential of enhancing fracture resistance and resistance to moisture assisted cracking.
10:15 AM - F5.3
Dielectric Recovery of Plasma Damaged Organosilicate Low-k Films by Combing UV and Silylation Treatments.
Huai Huang 1 , Hualiang Shi 1 , Junjing Bao 1 , Paul Ho 1 , Yifeng Zhou 2 , Jeremiah Pender 2 , Michael Armacost 2 , David Kyser 2
1 Microelectronics Research Center, The University of Texas at Austin, Austin, Texas, United States, 2 , Applied Materials, Sunnyvale, California, United States
Show AbstractPorous low-κ dielectrics are prone to plasma damage which is manifested as dielectric loss caused by methyl depletion and moisture uptake. In this study, we investigated the effect of UV and silylation treatments on dielectric recovery of oxygen plasma damage for porous organo-silicate glass (OSG) films. First, the effect of UV irradiation with thermal activation was investigated as a function of process parameters including UV dosage, incident angle, and substrate temperature. It was found that after a 300 sec UV treatment at 400°C, both the dielectric constant and the leakage current were partially recovered. The mechanism can be attributed to the removal of physisorbed water, -OH and C=O bonds although the surface hydrophobicity of the films was not completely recovered. To improve the dielectric recovery, we studied the effect of a CVD silylation process in combination with UV treatment, sequentially or simultaneously. Comparing with UV treatment alone, the combination of UV and silylation processes resulted in better recovery of the surface hydrophobicity and a further reduction of the leakage current. Under the same conditions, simultaneous treatments achieved better bulk and surface recovery than the sequential process. For sequential processes, the UV first followed by silylation treatment provided a better recovery in surface hydrophobicity and carbon concentration than the process in reverse sequence. These results indicated that UV treatments were able to promote the silylation process when applied simultaneously or before silylation. The mechanism of dielectric recovery for these processes will be discussed.
10:30 AM - F5.4
Super Low-k (k=2.1) and High-modulus (7 GPa) Interlayer Dielectrics With Controlled Multi-layer SiOCH Structure Formed by Damage-free Neutral-beam-enhanced CVD.
Toru Sasaki 1 , Shigeo Yasuhara 1 , Tsuromu Shimayama 2 , Kunitoshi Tajima 2 , Hisashi Yano 2 , Shingo Kadomura 2 , Masaki Yoshimaru 2 , Noriaki Matsunaga 2 , Seiji Samukawa 1
1 Institute of Fluid Science, Tohoku University, Sendai, Miyagi, Japan, 2 , Semiconductor Technology Academic Research Center, Yokoyama, Kanagawa, Japan
Show AbstractThe continuous shrinking of ultra-large-scale integrated (ULSI) circuits requires the use of materials with lower dielectric constant, i.e., k-value. One widely used low-k films is a SiOCH film formed by plasma-enhanced chemical-vapor deposition (PECVD). However, the k values of the film are generally between 2.7 and 3.0. To decrease the dielectric constant, we must control the excess dissociation of precursor in the CVD gas phase and understand the relationship between molecular-level structure and characteristics of the film. We have already proposed a structure-design method to form a super low-k SiOCH film by neutral-beam-enhanced CVD (NBECVD).The NBECVD apparatus consists of an ICP source and a process chamber connected through carbon apertures. During NBECVD, precursors are injected directly into the process chamber and adsorbed to the substrate surface. The NBECVD can eliminate irradiations of UV light and electrons which induce damage to the depositing film. In this way, the NBECVD is a damage-free deposition process. In addition, since the energy of the NB is controllable, the precursor can be decomposed at the selected bond portion. As a result, the molecular structure of the precursor can be reflected in the structure of the deposited film. Thus, we reported low-temperature formation of a super-low-k film by using DMOTMDS (dimethoxy-tetramethyl-disiloxane) as a precursor. This work demonstrated that NBECVD with DMOTMDS can provide a super low-k SiOCH film with k-value of 1.9, reasonably high modulus (4 GPa), higher water resistance, and higher thermal stability. In the present study, we investigated forming a multi-layer low-k film structure by NBECVD to obtain a film with both lower k-value (<2.2) and higher modulus (>6 GPa). A film with k-value of 1.9 and modulus of 4 GPa formed with DMOTDMS was used as a lower k-value layer. Conversely, a film with modulus is 9 GPa and k-value of 2.8 composed by MTMOS (methyl-trimethoxy-silane) was used as a higher modulus layer. These two different layers were deposited alternately, and five layers of stacked low-k film were formed by NBECVD. Two types of layered SiOCH film structures with thickness ratio of DMOTMDS and MTMOS layers of 65:35 and 43:57 were prepared. As a result, film properties could be precisely controlled by changing the ratio of film thickness. The low-k film with optimum ratio of DMOTMDS and MTMOS layers had a k-value of 2.1 and modulus of 7 GPa. We are also investigating the optimum film thickness ratio of the multi-layer structure by FEM simulation.
10:45 AM - F5.5
The Effect of UV Treatment on Mechanical and Dielectrical Properties of Ultra-low Dielectric Materials.
Bo-Ra Shin 1 , Kyu-Yoon Choi 1 , Hee-Woo Rhee 1
1 Chemical & Biomolecular Engineering, Sogang University, Seoul Korea (the Republic of)
Show Abstract Low dielectric materials (low-k) have promoted the evaluation of microelectronics as interlayer dielectrics (ILD) over the years. However, continuous shrinkage of the device and requirement for higher performance needed new materials which can replace the low-k. The appropriate nanoporous ultra-low dielectric materials having lower dielectric constant and stronger mechanical properties are being developed as a promising candidate. However, both of the properties are incompatible, in particular, the pores introduced to reduce the dielectric constant adversely affect the mechanical properties. For mechanical enhancement of the nanoporous dielectrics, UV treatment is one of the most effective methods because it has chemical and structural effects on the nanoporous dielectrics by breakage and rearrangement of silicon bond structures. In this study, we prepared nanoporous dielectric film by using organosilicate matrix and chemically reactive porogens. The organosilicate matrix was copolymer of methyl trimethoxysilane (MTMS) and 1,2-bis(triethoxysilyl) ethane (BTESE), and the porogen was trimethoxysilyl xylitol (TMSXT). The TMSXT was synthesized by allylation and hydrosilylation and the trimethoxysilyl terminal groups helped make uniform pores and mechanically strong matrix. UV lights of 254 and 352 nm wavelengths with 7 mW/cm2 intensity were irradiated during thermal curing on the nanoporous dielectrics for various times (5, 10, 30 min). As a result, the UV treatment improved the dielectrical properties as well as mechanical properties. Its elastic modulus of UV-cured one increased to 10.7 GPa at k = 2.16. This is because network structures and Q structures formed by increased reactivity of Si-OH and Si-OR groups. UV irradiation also broke Si-CH3 groups of MTMS, which made more free volume into dielectrics at the same porogen loading. Therefore, UV treatment resulted in the increased porosity but decreased dielectric constant in spite of the formation of denser network structures.
11:30 AM - **F5.6
Scaling of Low-k Dielectrics: A Bumpy Road.
Mikhail Baklanov 1 , Larry Zhao 2 , Bart Vereecke 1
1 , IMEC, Leuven Belgium, 2 , INTEL Corporation, Leuven Belgium
Show AbstractIntensive research carried out during the last decade demonstrated that incorporation of porosity into hybrid dielectrics (carbon doped silicon dioxide) is the most efficient way to obtain ultra-low-k materials potentially suitable for integration into ULSI devices. However, the integration of these materials is still showing many challenges that need to be solved. Integration of porous ultra-low-k materials is becoming even more difficult with the device scaling. Decrease of the k-values needs more porosity. Increase of the porosity increases the pore size and the materials are becoming more chemically stable and mechanically weak. Decreased resistance to plasma and CMP damage is related to higher accessibility of low-k internal surfaces. As a result, the depth of processing damage may become comparable with the feature sizes. All these issues will be discussed using experimental data obtained by low-k materials characterization and integration into interconnect structures. Special attention will be paid to experimental results and theoretical study of low-k deposition, UV curing, qualitative and quantitative description of plasma damage, development of damage free processes and challenges related to low-k and device scaling. It will be shown that some of recently developed organic low-k materials allow to address these challenges. Although most of the results are based on traditional experimental techniques and approaches, new results obtained using advanced test structures like “p-cap” will be reported. This test structure allows to characterize intrinsic dielectric properties with minimum modification of the dielectric by process conditions, therefore, it is very valuable for initial characterization of materials that have potential for integration.
12:00 PM - F5.7
Molecular Dynamics Study of Amorphous Carbon Growth by Glancing Angle Deposition.
Minwoong Joe 1 , Kwang-Ryeol Lee 1
1 Computational Science Center, Korea Institue of Science and Technology, Seoul Korea (the Republic of)
Show AbstractEmploying the classical molecular dynamics simulation, the structure of amorphous carbon film and its related properties at various glancing angles are investigated. At a glancing angle and low deposition energy condition, more porous and subsequently low-k film is constructed by the glancing angle deposition. Also, shadowing effect at this glancing incidence of carbon atoms tends to cause columnar structures. We systematically study the film properties by altering the deposition energy (1-300 eV) and the angle of incidence (0°- 90°). For quantitative analysis of the structure, we calculate stress, sp hybridization ratio, pair correlation function, atomic density, volume fraction (porosity), and dielectric constant of the obtained films. Our results provide an atomic-level understanding about the dependence of incidence angle and deposition energy on the structures and properties of the films, which is useful in finding optimum growth condition of a novel low-k materials based on the mixture of amorphous carbon and molecular void.
12:15 PM - F5.8
Stiffening Mechanism in Methane-bridged Organosilicate Glasses: A Molecular Dynamics Study.
Han Li 1 , Jan Knaup 2 , Efthimios Kaxiras 1 2 3 , Joost Vlassak 1
1 School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 2 Department of Physics, Harvard University, Cambridge, Massachusetts, United States, 3 , Ecole Polytechnique Federale de Lausanne, Lausanne Switzerland
Show AbstractContinued miniaturization of microelectronic devices and advanced interconnection technologies have demanded interconnect dielectrics with reduced dielectric constant. While new materials and processes are being introduced that have successfully driven the insulator dielectric constant down to 2.0, the significantly degraded mechanical properties of the materials remain as major roadblock for their successful integration in volume production. It has recently been recognized that methane and ethane bridged organosilicates possess significantly improved mechanical strengths in comparison with conventional organosilicates where carbon atoms exist mainly in dangling methyl groups. However, quantitative insights in understanding the reinforcing mechanism at molecular level remain elusive. In this paper, we focus on understanding how the elastic properties of methane-bridged organosilicates are correlated with their molecular network structure using molecular dynamics simulation. To elucidate quantitatively the share of contribution from various structural factors, we choose fully networked amorphous silica as the pristine model. By gradually replacing some of the oxygen network atoms with methane units, we demonstrate for the first time that the bulk modulus increase monotonically from that of pure silica to about three times higher as all oxygen atoms are replaced. The stiffening is achieved via the mechanism that more elastic deformation is accommodated through stretching/compressing of Si-O bonds and less through the bending of Si-O-Si as carbon concentration increases. Meanwhile, mass density of the material decreases nearly linearly with carbon concentration, leading potentially to a reduction in the dielectric constant of more than 30%. The role of dangling methyl group will also be discussed.
12:30 PM - F5.9
Barrier Metal Ions Drift into Porous Low-k Dielectrics Under Bias Temperature Stress.
Ming He 1 , Ya Ou 1 , Pei I Wang 1 , Lakshmanan Vanamurthy 2 , Hassaram Bakhru 2 , Toh Ming Lu 1
1 Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 College of Nanoscale Science and Engineering, State University of New York at Albany, Albany, New York, United States
Show AbstractTa family has been used as barrier to prevent Cu diffusion into interlayer dielectric (ILD) in advanced integrated circuit (IC) applications. To be a viable barrier material, not only should it prevent Cu diffusion into the dielectric, but the barrier material itself should also be stable and not penetrate into the dielectric. However, our recent experiments demonstrated that a larger flatband voltage shift (ΔVFB) would occur for Ta on porous low k dielectric MIS capacitor than that of Cu on porous low k capacitor after the same and moderate bias temperature stress (BTS) condition [1]. To explain the origin of the flatband voltage shift difference, we have proposed that there are more Ta ions drift into porous low k than Cu under the same BTS condition. However, this explanation has generated some controversy and alternative arguments, such as proton drift (from moisture) [2] and dielectric polarization [3], have been proposed. In this talk, we report for the first time the existence of Ta ions inside porous methyl silsesquioxane (MSQ) in a Ta/MSQ/Si capacitor after BTS, by using Secondary Ion Mass Spectrometry (SIMS) backside sputter depth profile technique. On the other hand, for the Cu/MSQ/Si capacitor, depth profiles show no observable increase of Cu inside MSQ after the same BTS condition. These results confirm our proposal that there are more Ta ions drift into porous low k dielectric than Cu under the same BTS condition, and these Ta ions are the reason for the flatband voltage shift.[1] P.-I. Wang, J. S. Juneja, Y. Ou, T. M. Lu, and G. S. Spencer, J. Electrochem. Soc. 155, H53 (2008).[2] I. Ciofi, Z. Tökei, G. Mangraviti, and G. Beyer, Mater. Res. Soc. Symp. Proc. 2008 Spring Meeting, San Francisco, CA, 1079 (2008).[3] K.-L. Fang and B.-Y. Tsui, J. Appl. Phys. 93, 5546 (2003).This work is supported in part by Semiconductor Research Corporation (SRC).
12:45 PM - F5.10
Impact of Restoration Treatments Studied by Dielectric Spectroscopy Correlate With Physico-chemical Analysis.
Christelle Dubois 1 , Alain Sylvestre 1
1 , CNRS, Grenoble France
Show AbstractDuring the integration process, the low k porous material SiOCH goes through many steps which lead to the degradation of the material properties. After a chemical mechanical polishing process (CMP) the dielectric properties are damaged and leakage currents increase due to water and surfactants adsorption. The dielectric permittivity is degraded of about 25% in the whole range of the investigated frequency (10-1 Hz – 100 KHz). In a same way, the dielectric losses increase at the lowest frequencies. In previous works we studied the restoration treatments efficency to remove surfactants and water adsorbed during the CMP process. These treatments carried out after CMP induces a reduction of the leakage current and the dielectric permittivity.We now investigate the impact of these treaments on the material. The porous material SiOCH was studied as deposited and after undergoing restoration treatments which consist in an annealing at moderate temperature under N2 and UV exposure. Dielectric measurements performed on the as deposited SiOCH from -100°C to 150°C with a step of 25°C on a wide range of frequency 10-1 -105Hz, exhibit a relaxation peak. The mechanism which probably causes this dielectric relaxation has an activation energy of 25-30kJ/mol and is associated to the motion of molecules present in the materials. After restoration treatment the dielectric properties are improved, however the position and the amplitude of the peak are modified, which means that some changes occur in the material during annealing. Physico-chemical analysis are performed to explain the impact of restoration treatment on the material.
F6: Novel Low-<i>k</i> Materials
Session Chairs
Wednesday PM, April 07, 2010
Room 2010 (Moscone West)
2:30 PM - **F6.1
Molecularly Reinforced Sol-gel Glasses: Preparation, Characterization and Integration Studies.
Willi Volksen 1 , Geraud Dubois 1 , Teddie Magbitang 1 , Victor Lee 1 , Robert Miller 1 , James Doyle 2 , Nicholas Fuller 2 , Sebastion Engelmann 2 , Maxime Darnon 2 , Michael Lofaro 2 , Stephan Cohen 2 , Sampath Purushothaman 2 , Hisashi Nakagawa 3 , Youhei Nobe 3 , Terukazu Kokubo 3
1 , IBM Almaden Research Center, San Jose, California, United States, 2 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 3 , JSR Tsukuba Research Laboratories, Tsukuba, Ibaraki, Japan
Show AbstractReinforcement of sol-gel glasses at the molecular level via carbon-bridging units between silicon atoms has been previously reported to yield organosilicate network structures with fracture energy values significantly higher than those reported for dense SiO2 [1,2]. This observation suggested that mechanical properties of this unique class of materials fall in between conventional glasses and organic polymers. Unlike the power dependence of traditional organosilicates , these materials exhibit a linear decay in Young’s modulus with decreasing density (increasing porosity). As a result, highly porous films with good mechanical properties (high modulus and good crack resistance) are readily prepared. Such properties are critical for microelectronic applications as porous organosilicates will constitute the insulating layer in future device generations [3,4].In this presentation we will be describe the formulation of a new organosilicate resin developed jointly with JSR Corporation, called LKD 6504, with various porogens and associated stability studies for high solids content solutions. In addition, thorough characterization of films with porosity levels approaching 50%, i.e. k = 2.0, as well as integration studies addressing critical parameters, such as interfacial adhesion, CMP behavior and etch characteristics, will be discussed.[1] G. Dubois, W. Volksen, T. Magbitang, R.D. Miller, D. Gage, R. Dauskardt, Adv. Materials, 2007, 19 (22), 3989-3994.[2] G. Dubois, W. Volksen, T. Magbitang, M. Sherwood, R.D. Miller, D. Gage, R. Dauskardt, J. Sol-Gel Sci. & Techn., 2008, 48 (1-2), 187-193.[3] G. Dubois, W. Volksen, R.D. Miller, Dielectric Films for Advanced Microelectronics, M. Baklanov, K. Maex, M. Green (Editors), Wiley, 2007, Chapter 2.[4] W. Volksen, R.D. Miller , G. Dubois, Low-K Dielectric Materials, Chemical Reviews, 2010, in press.
3:00 PM - F6.2
Silsesquioxane-based Photopatternable Porous Low-k Dielectric Materials.
Jitendra Rathore 1 , Blake Davis 1 , Phillip Brock 1 , Ratnam Sooriyakumaran 1 , Robert Miller 1 , Qinghuang Lin 2 , Nelson Alshakim 1
1 Advanced Organic Materials Div, IBM Almaden Research Center, San Jose, California, United States, 2 , IBM Watson Research Center, Yorktown Heights, New York, United States
Show AbstractConventional wiring levels in an integrated circuit are formed by depositing an interlevel dielectric layer, patterning a photoresist layer formed on the dielectric layer, etching trenches in the dielectric layer, removing the photoresist and filling the trenches with metal. This is an expensive and time-consuming process. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations. Photopatternable low-k dielectric materials hold the potential to reduce the cost and complexity of the integration process by reducing the number of steps. In this regard, we have developed silsesquioxane based low-k dielectric materials, which can form a negative tone photo-patternable dielectric formulation that becomes porous upon curing. Patternwise exposure of a layer of the formulation directly forms a cross-linked patterned dielectric layer (without the use of photoresist based lithography or etching of the dielectric layer) after development. After curing the patterned dielectric layer, a porous low dielectric constant (k) patterned dielectric layer is produced. Dielectric constant as low as k~2.4 was achieved with current materials with retention of appreciable elastic modulus (E > 4.0 GPa).
3:15 PM - F6.3
Potential of the Ultra-thin Layer Fabricated by Wet-process as a Pore-seal for Porous Low-k Films.
Shoko Ono 1 , Kazuo Kohmura 1 , Hirofumi Tanaka 1 , Kentaro Nakayama 1 , Akifumi Kagayama 1 , Toshihiko Tsuchiya 2 , Makoto Nakaura 2 , Osamu Matsuoka 1 , Toshihiko Takaki 1 , Kou Maekawa 1
1 R&D center, Mitsui Chemicals, Inc., Sodegaura, Chiba Japan, 2 Analysis Research Lab. , Mitsui Chemical Analysis & Consulting Service Inc. , Sodegaura, Chiba Japan
Show AbstractLSI technology for 32nm node and beyond needs ultra Low-k films having k-value below 2.1. In order to reduce the dielectric constant, porous Low-k film is indispensable and widely studied. However, porous Low-k film is sensitive to process-induced damages caused by plasma and metallization process, because such stimuli may defuse via open pore of film. The purpose of our work is the development of pore-seal technology for Low-k film surface in order to achieve porous Low-k / Cu damascene process.We introduce here that the ultra-thin layer fabricated by wet-process drastically suppresses the diffusion of metal into porous low-k film in metallization process. We chose physical vapor deposited copper, PVD-Cu, as a probe of diffusion of metals. The depth of copper diffusion into porous low-k films was evaluated as follows. Porous Low-k film (Mitsui Chemicals, Inc., pore-size 2.5 nm) was used in this work and was covered with ultra-thin layer using spin coating apparatus. On the ultra-thin layer, a copper film, 100 nm in thickness, was sputtered . After Cu sputtering, the diffusion of Cu into porous Low-k film was observed using cross-sectional transmission electron microscopy (TEM, JEM-2200FS, JEOL Co., Ltd., Japan). In the case of without the ultra-thin layer, several clusters, 2-3 nm in size, were observed in the range of 30 nm in depth from the surface of porous low-k film. The cluster was identified as cupper according to electron energy loss spectrum (EELS) analysis. On the contrary, with the ultra-thin layer, no clusters was observed. It means that the ultra-thin layer plays a role to prevent the PVD-Cu diffusion. Thickness of the ultra-thin layer is about 1 nm estimated by cross-sectional TEM imaging. This result shows that the ultra-thin layer has a potential as a pore-seal for porous low-k film. Adhesion between the ultra-thin layer and Cu layer after annealing at 350 degree C in forming gas was estimated by tape peel method. The abrasion between ultra-thin layer and Cu was not detected. We believe this unprecedented method, which we propose here, opens the door to LSI technology for 32nm node and beyond.
3:30 PM - F6.4
Molecular Modeling and Design of Low-k Hybrid Glasses.
Mark Oliver 1 , Geraud Dubois 2 , Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States, 2 , IBM Almaden Research Center, San Jose, California, United States
Show AbstractThe development of advanced spin-on and CVD low-k glasses with acceptable mechanical properties requires engineering of the glass molecular and nanopore structure at a level not possible with existing predictive models. We describe the development of computational methods to address the fundamental relationship between molecular structure and resulting mechanical and fracture properties of organosilicate glasses. Using a new simulated annealing approach, large distortion-free hybrid glass networks with well-controlled network connectivity can be generated. With this capability along with a novel fracture model and molecular dynamics simulations of elastic deformation, we elucidate the critical effect of network connectivity on mechanical properties. The accuracy of our computational tools is confirmed through comparison to synthesized low-k films where the molecular structure and connectivity is carefully controlled and characterized. The strengthening effects of incorporating molecular bridges in the glass network as opposed to terminal methyl groups is modeled and described. Having predictive models for how molecular structure affects mechanical properties offers the opportunity for computational design of new glasses and provides quantitatively accurate rationale for guiding precursor selection. Thus in addition to the fundamental insights gained regarding structure-mechanical property relationships, we will present our efforts to apply these tools to design new neat and nanoporous glasses with exceptional mechanical properties and low density.
3:45 PM - F6.5
Structural and Property Characterization of Four Periodic Mesoporous Organosilica (PMO) Thin Films for Applications as Low-dielectric-constant Materials.
Wendong Wang 1 2 , Daniel Grozea 2 , Douglas Perovic 2 , Geoffrey Ozin 1
1 Chemistry, University of Toronto, Toronto, Ontario, Canada, 2 Materials Science and Engineering, University of Toronto, Toronto, Ontario, Canada
Show AbstractUsing the most cutting-edge techniques, such as Ellipsometric Porosimetry and Surface Acoustic Wave Spectroscopy, we obtain values of porosity, pore size distribution, mesopore wall thickness, film density, dielectric constant, and Young's modulus for four different periodic mesoporous organosilica thin films. These four PMOs are ethane, ethene, methane, and 3-ring PMOs. With the same surfactant to silicon molar ratio, ethene PMO is found to have the highest out-of-plane Young's Modulus around 3.5GPa, and methane PMO the highest in-plane Young's Modulus 28GPa. The relative dielectric constants of all PMO films are below 2.
4:00 PM - F6: Novel low k
BREAK
F7: Novel Patterning Techniques for Low <i>k</i>
Session Chairs
Wednesday PM, April 07, 2010
Room 2010 (Moscone West)
4:30 PM - **F7.1
The Direct Patterning of Organosilicate Interconnect Materials by Nanoimprint Lithography.
Christopher Soles 1 , Hyun Wook Ro 1
1 Polymers Division, NIST, Gaithersburg, Maryland, United States
Show AbstractOrganosilicate or silsesquioxane (SSQ) films are widely used in a range applications, including nanocomposites, scratch resistant coatings, barrier coatings, biological devices, porous separation media, optical films or coatings, semiconductor interconnect insulators, and high resolution e-beam resist materials. Some of the attributes which lead to this widespread use includes the ease with which they can be processed into high quality films and coatings, the ability of these films and coatings to support high levels of porosity, and their intrinsic resistance to high temperatures and aggressive chemical environments. Recently there has been interest in patterning nanoscale functional devices directly into SSQ materials using nanoimprint lithography (NIL). Here we explore the use of NIL as a high resolution lithography to directly pattern SSQ materials. The primary target for this work is to simplify fabrication processes and significantly reduce the manufacturing costs for semiconductor interconnect structures. However, the prospect of mechanically forging these materials, especially in their porous form, into nanoscale patterns raises concerns regarding their physical integrity and pore structure. So we have developed critical dimension small angle X-ray scattering and specular X-ray reflectivity methods to verify that an excellent fidelity of the pattern transfer process can be achieved, with minimal pattern shrinkage or distortion. Furthermore, we have also developed the measurement techniques to characterize the porosity characteristics of SSQ patterns, and thus their dielectric constants that are critical to the performance of an interconnect structure. X-ray porosimetry (XRP) is used quantify the average density, the porosity, and the wall density of the material between the pores of these imprinted patterns. All of these parameters characterized by XRP can be resolved as a function of vertical height through the pattern. In addition, positron annihilation lifetime spectroscopy (PALS) measurements are described to quantify the pore size distributions and the degree of pore interconnectivity in the patterned material. Finally, the porosity characteristics determined by XRP and PALS are correlated with high resolution transmission electron microscopy (TEM) images of the pattern cross section to obtain a complete picture of how the imprint process affects the porosity of these materials. Examples will be shown where the porosity level is pushed to over 50 % by volume, well into the ultralow-k regime where the expected dielectric constants will be less than 1.8. In addition to the interconnect applications, we will also show how these SSQ materials can be used to make high resolution daughter NIL molds from an imprint master or template. These daughter molds can be used to then directly imprint a range of materials, including both thermal and UV cross-linkable materials, thereby extending the life of the imprint master.
5:00 PM - **F7.2
Novel Solutions for Interconnect Challenges: Directly Patterned ULKs Using Existing Resist Platforms and Sacrificial Adhesion Layers for Single Step Cu Metallization.
James Watkins 1
1 Polymer Science and Engineering, University of Massachusetts, Amherst, Massachusetts, United States
Show AbstractNovel approaches to directly patterned ULK films and single step deposition of Cu using sacrificial adhesion layers will be discussed. Our approach to mesoporous silicates for ULKs involves the infusion and selective condensation of organosilicate precursors within one phase domain of a preformed block copolymer template dilated with supercritical carbon dioxide. The template is then removed to produce the mesoporous oxide. The first-generation of templates yielded films dielectric constants as low as 1.8. A film with k = 2.2 was selected for further evaluation and found to survive CMP in a planar test stack. Three recent extensions to the technique that significantly enhance film properties and integration strategies will be discussed. Of specific interest is direct pattering of interlayer dielectric films using optical lithography for selective area exposure of templates containing photo acid generators prior to precursor infusion. Removal of the template then yields a directly patterned mesoporous film, eliminating the need for etching and substantially compressing the number of processing steps. The templates used are based on conventional 248 nm and 193 nm resist platforms and both positive and negative tone patterning is possible. Recent feasibility experiments using off the line 193 nm resists indicate that sub 100 nm resolution is readily achieved. Reactive deposition of Cu via supercritical fluid deposition offers opportunities for meeting the metallization demands of sub 32 nm interconnects. We previously reported that Cu deposition from supercritical carbon dioxide yields single step filling of features directly on barriers without the need for seed layers. Here we report that the adhesion of Cu films deposited from CO2 can be dramatically improved by the use of sacrificial poly(acrylic acid) (PAA) adhesion layers prepared on the substrate via vapor deposition/polymerization prior to metallization. Detailed analysis indicates the PAA adhesion layer quantitatively decomposes at the deposition conditions, and no trace of the polymer film can be detected at the Cu/substrate interface by x-ray photoelectron spectroscopy (XPS). Films deposited using the adhesion layer pass the scribed tape test on all substrates studied and quantitative measurements via 4 pt bending indicate adhesion energies in excess of 5 J/m2, which meets threshold for integration.
5:30 PM - F7.3
Multi-level Integration of Photo-patternable Low-k Material into Advanced Cu BEOL.
Qinghuang Lin 1 , Shyng-Tsong Chen 2 , Alshakim Nelson 3 , P. Brock 3 , S. Cohen 1 , B. Davis 3 , N. Fuller 1 , R. Kaplan 4 , R. Kwong 4 , E. Liniger 1 , D. Neumayer 1 , J. Patel 1 , H. Shobha 2 , R. Sooriyakumaran 3 , S. Purushothaman 1 , T. Spooner 2 , R. Miller 3 , R. Allen 3 , R. Wisnieff 1
1 , IBM T.J. Watson Research Center, Yorktown Heights , New York, United States, 2 , IBM Systems and Technology Group, Albany, New York, United States, 3 , IBM Almaden Research Center, San Jose, California, United States, 4 , IBM Systems and Technology Group, Hopewell Junction, New York, United States
Show AbstractThe continuous down scaling of semiconductor devices, while improving performance and increasing device density, has been increasingly achieved at the expense of higher complexity and manufacturing costs. These highly-complex and high-cost processes are evident in almost the entire semiconductor fabrication process beyond 65 nm technology nodes, from lithography, FEOL, to BEOL. They include replacement gate process for high-κ/metal gate in FEOL and double patterning in lithography at the 45 nm technology node. In BEOL, the introduction of low-κ materials at the 90 nm technology node has also significantly increased process complexity due to the need for several sacrificial layers to form dual-damascene Cu BEOL structures. This trend of increasing process complexity is expected to continue in the fabrication of future generations of computer chips.In this paper, we wish to update our work on a simple, low-cost, novel patternable low-κ dielectric material concept that was first introduced in 2009. A photo-patternable low-κ dielectric material combines the functions of a traditional resist and a dielectric material into one single material. It acts as a traditional resist during patterning and is subsequently converted to a low-κ dielectric material during a post-patterning curing process. No sacrificial materials (separate resists or hardmasks) and their related deposition, pattern transfer (etch) and removal (strip) are required to form dual-damascene BEOL patterns. As a result, dual-damascene BEOL structures can be formed with remarkable simplicity and efficiency using this novel approach. We will report on the demonstration of multi-level dual-damascene integration of a novel photo-patternable low-κ dielectric material into advanced Cu BEOL. This κ=2.7 photo-patternable low-κ material is based on the industry standard SiCOH-based (silsesquioxane polymer) material platform and is compatible with 248 nm optical lithography. Multi-level integration of this photo-patternable low-κ material at 45 nm node Cu BEOL fatwire levels has been demonstrated with very high electrical yields using the current manufacturing infrastructure. Photo-patternable low-κ materials capable of higher resolution with 193nm optical lithography will also be discussed. AcknowledgementsThe authors would like to thank valuable assistance from numerous IBM colleagues, including the Microelectronics Research Laboratories at IBM Watson Research Center, IBM Systems and Technology Group in Fishkill and Albany and IBM Almaden Research Center. We are also grateful for insightful discussions with Drs. M. Angyal, G. Biery, D. Edelstein, J. Gambino, T. Ivers, W. Landers, D. Long, R. Varanasi and T. Standaert. We also thank JSR Corp. for providing material components and material scale-up.
5:45 PM - F7.4
Patterning Capabilities of 40-nm Contact Holes at 80-nm Pitch: EUV vs. Line/Space Double Exposure Immersion Lithography.
Frederic Lazzarino 1 , Vincent Truffert 1 , Joost Bekaert 1 , Jean-Francois de Marneffe 1 , Steven Demuynck 1 , Mieke Goethals 1 , Herbert Struyf 1
1 , IMEC, Leuven Belgium
Show AbstractExtreme ultraviolet lithography (EUVL) is one of the leading candidates for the 22-nm node device manufacturing. However, the technique has several challenges to overcome before being qualified for production. In this context, novel approaches such as immersion lithography using a line/space (L/S) double exposure have been explored in order to provide 40-nm contact holes (CH) at 90-nm pitch and below.In this work, we mainly focus on the etch patterning capability of dense CH obtained either by using EUVL or immersion lithography with the L/S imaging method. Two different hard mask strategies have been used. A TiN layer has been initially selected and combined with two L/S imaging approaches. The first approach consists in reversing a pattern of pillars into a pattern of CH by using an overcoat. This approach involves several process steps including three etching steps in order to get a pattern of CH that can be etched. Despite the operational complexity of the technique, 40-nm CH at 80-nm pitch have been etched. The second approach consists in a negative tone development to create directly CH instead of pillars. There is no intermediate step and the technique is therefore more attractive. Besides, the etch patterning capability has been demonstrated and the technique is now considered as a good alternative to get dense CH. As a result, for some applications, we combined it with a carbon mask layer to substitute the TiN. This allowed us to start some inexpensive preliminary developments on advanced CH patterning and metallization. The etch process developed in this way is then transferred onto EUV wafers. Two examples are presented and discussed based on CD-SEM and X-SEM analysis.Finally, it was shown that 40-nm CH at 90-nm pitch and below can be obtained by using either EUVL with a single patterning approach or immersion lithography with a L/S double exposure approach; the CH etch capability has been successfully demonstrated.
F8: Poster Session II
Session Chairs
Azad Naeemi
Alshakim Nelson
Dorel Toma
Thursday AM, April 08, 2010
Salon Level (Marriott)
9:00 PM - F8.1
Investigation of Joule Heating Effect in Various Stages of Electromigration in Flip-chip Solder Joints by Infrared Microscopy.
Hsiang Yao Hsiao 1 , Chih Chen 1
1 , Department of Materials Science and Engineering, National Chiao Tung University, Taiwan Taiwan
Show AbstractThe Joule heating effect at various stages of electromigration of flip-chip Sn3.5Ag solder joints was investigated under a current of 0.5 Amp at 100 °C. During various stages of electromigration, voids may form and propagate and Joule heating effect may vary at different void sizes. To verify the void nucleation and propagation on Joule heating effect during electromigration process, the solder bump was stressed for different lengths of time and then examined by Kelvin bump probes and infrared microscopy. We found that voids started to form at approximately 1.2 times of the initial bump resistance. Then the voids propagated when the bump resistance increased. In addition, the temperature of the solder joints is also increased with the bump resistance and the increase of current stressing time. When the bump resistance lowly increased to 5.0 times of the initial values, the temperature of the solder bump raised unnoticeablely. In the last stages, the temperature of the solder bump increased rapidly due to the bump resistance increased and local Joule heating effect.
9:00 PM - F8.10
Characterization of in-situ Sheet Resistance and Work Function for Ultra-thin Metal Films.
Na-Hyun Kwon 1 , Kijung Park 1 , Bin Hwang 1 , Kwun Nam Hui 1 , Young-Rae Cho 1
1 School of Materials Science and Engineering, Pusan National University, College of Engineering, Pusan, Geumjeong-Gu, Korea (the Republic of)
Show AbstractThe trend in electronic devices has been moving to higher density, smaller size and thinner shape. The sizes of aluminum (Al) metal lines for interconnections in the electronic devices have also been moving to the direction of ultra-thin and narrower width. In this study, ultra-thin Al metal line was patterned by photolithography on glass wafer, and then characterized by the in-situ 4-point probe measurement. Sheet resistance of the ultra-thin Al films was measured by the in-situ 4-point probe, which was then used to determine the coalescence thickness. For the metallic Al layer, the critical thickness was found to be 120Å. Ultraviolet photoelectron spectroscopy (UPS) was applied to measure the work function of the 20 Å, the 120 Å and the bulked Al layers. The work function of the 120 Å thin and the bulked Al layers were 4.2 eV and 4.28 eV, respectively. However, the work function of the 20 Å ultra-thin Al metal could not be measured. The results clearly elucidated that the work function was changed when the thickness of materials reached the atomic range. The finding from this study is very important which provides insight into investigation of the mechanism of electron transport in an ultra-thin conducting layer in nanoscale electronic devices and the study of interface properties in ultra small device such as organic light emitting diode.
9:00 PM - F8.11
Flexible Anisotropic Pressure Sensor and Nanogenerator Based on PVDF and P(VDF-TrFE) Nanofiber Webs Prepared Through Electrospinning.
Dipankar Mandal 1 , Sun Yoon 1 , Kap Jin Kim 1
1 Advanced Polymer and Fiber Materials, Kyung Hee University, Yongin-si, Gyeonggi-do, Korea (the Republic of)
Show AbstractPolyvinylidene fluoride (PVDF) and its copolymer P(VDF-TrFE) films exhibiting piezo- and pyroelectric behavior have been investigated by many researchers in the last three decades for varying applications such as sensors, transducers, etc. However, due to several disadvantages such as non-breathability and non-selectivity of directional deformation by external pressure and elongation, PVDF and P(VDF-TrFE) films are not suitable for pressure sensors for a smart and intelligent garment capable of detecting the position and magnitude of external physical impact.In this work, we have adopted a method, namely electrospinning, by which we can prepare PVDF and P(VDF-TrFE) nanofiber webs. This simple and scale-up processing technique has many advantages for touch and pressure sensor applications, because a single-step electrospinning process can eliminate the need for direct-contact or corona poling to induce spontaneous dipolar orientation. In addition to that, flexibility and air permeability of the nanofiber webs make them more convenient for practical smart garment applications.When PVDF or P(VDF-TrFE) film is used as a pressure sensor attached to a smart garment, the output signal comes from elongational deformation caused by motion artifact such as stretching or twisting while wearing it as well as real external physical impact. Therefore, one cannot abstract the real external impact component. However, when PVDF or P(VDF-TrFE) nanofiber web having very high z-directional selectivity is used as a pressure sensor for a smart garment, the output signal comes preferentially from real external physical impact, not from motion artifact.In addition to touch and pressure sensors for a smart garment, PVDF and P(VDF-TrFE) nanofiber webs can be used as a generator as well. Recently some researchers have reported a basic concept of piezoelectric nanogenerator based on zinc oxide (ZnO) nanowire arrays and PZT. But they have some limitations for real application due to rigidity, heaviness, brittleness, etc. In contrast with such researches, we have adopted piezoelectric polymer based nanoweb systems which have advantages such as flexibility, durability, large area fabrication, etc.We have used conductive PEDOT coated PVDF nanoweb as top and bottom electrodes of PVDF or P(VDF-TrFE) nanoweb based pressure sensor and generator to maintain air-permeability of a smart garment. More detailed electrical properties of PVDF or P(VDF-TrFE) nanoweb based pressure sensor and generator will be discussed in the presentation.Acknowledgement : This work was supported by the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea government (MEST) (R11-2005-065) and Industrial Source Technology Development Programs (funded by the Ministry of Knowledge Economy (MKE, Korea)).
9:00 PM - F8.12
Asymmetric Texture Evolution of the Gold Wire and its Effect on Leaning Problem.
Seoung-Bum Son 1 , Suk Hoon Kang 1 , Do Hyun Kim 1 , Jung Han Kim 1 , Hyunchul Roh 1 , Jong Soo Cho 1 2 , Jeong-Tak Moon 2 , Hee-Suk Chung 1 , Kyu Hwan Oh 1
1 , Seoul National Univ., Seoul Korea (the Republic of), 2 , MK electron, Yongin-Si, Gyeong gi-do Korea (the Republic of)
Show AbstractGold wire mainly performs interconnecting between IC chips for electrical conduction. After gold wires are bonded, it is found that a few wires are leaned to other wires. Unexpected connection between wires causes a short-circuit problem, and this leads to IC chips failure. In this research, FEM and EBSD methods are used to analyze how wire leaning problem is occurred. By observing SEM images of drawing dies, it is found that dies have unsymmetrical shapes near wire reduction area which can lead to asymmetrical deformation of wire. By EBSD analysis, it is turned out that RD//<100> texture is off center in the wire which is supposed to be exact in the center of the wire in the case of general cold drawn gold wire. Considering RD//<111> texture is typical drawing texture and RD//<100> texture is undeformed texture, it is thought that out of centered RD//<100> texture means asymmetric deformation of wire in the drawing process. After that, elastic modulus of each orientation is calculated and applied to FEM analysis. Through FEM, under applying tensile stress, we changed the location of RD//<100> in the gold wire from center to surface, and studied that how location of <100>orientation has effect on leaned shapes of bonded gold wire.*.Acknowledgement -. This research (paper) was performed for “the Material & Component technology development program” funded by the Ministry of Knowledge & Economy (MKE) of Korea.
9:00 PM - F8.13
Direct Observation of Emission of Partial Dislocations From Incoherent Twin Boundaries in Copper.
Hsin-Ping Chen 1 , Wen-Wei Wu 3 , Chien-Neng Liao 2 , Lih-Juann Chen 2 , King-Ning Tu 1
1 Materials Science and Engineering, University of California, Los Angeles, Los Angeles, California, United States, 3 Materials Science and Engineering, National Chiao Tung University, Hsinchu Taiwan, 2 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Show AbstractThe mechanism of nano-twin boundaries migration in copper under electric current stressing has been resolved by using in-situ ultrahigh vacuum transmission electron microscopy. Both coherent twin boundaries (CTBs) and incoherent twin boundaries (ITBs) migration kinetics involves the emission of partial dislocations from the stressed incoherent twin boundaries in copper by electric force. The glide of any of Shockley partial dislocations changes the (111) plane stacking caused the migration of CTBs. On the other hand, the migration of ITBs is promoted by the cooperative motion of a group of atoms in the ITB structure and the different local stress states at ITBs.
9:00 PM - F8.14
Towards the Understanding of Resistive Contrast Imaging in in-situ Dielectric Breakdown Studies Using a Nanoprober Setup.
Konstantina Lambrinou 1 , Thomas Hantschel 1 , Kai Arstila 1 , Stephan Kleindiek 2 , Andreas Rummel 2 , Zsolt Tokei 1 , Kristof Croes 1 , Marianna Pantouvaki 1 , Piotr Czarnecki 1 , Ingrid De Wolf 1 4 , Wilfried Vandervorst 1 3
1 , IMEC, Leuven Belgium, 2 , Kleindiek Nanotechnik GmbH, Reutlingen Germany, 4 Dept. Metallurgy & Materials Engineering, KU Leuven, Leuven Belgium, 3 IKS-Dept. Physics, KU Leuven, Leuven Belgium
Show AbstractResistive Contrast Imaging (RCI) is a scanning electron microscopy (SEM) technique, where the relative resistance map of the structure under investigation is created by measuring absorbed SEM electron beam current as a function of the beam position [1, 2]. Important difference of RCI compared to the more common Electron Beam Induced Current (EBIC) technique is that RCI does not facilitate current amplification in an active test structure but the measured currents are only a fraction of the primary electron beam. This necessitates the use of high-gain current-voltage amplifier with a limited bandwidth, making RCI prone to various imaging artifacts.
The purpose of this work is to deepen the understanding of RCI image generation in studies involving failure site localization, such as in Time-Dependent Dielectric Breakdown (TDDB) of low-k dielectrics. Typical test structures in this work included 50-nm wide and 1-100-µm long parallel conductor lines embedded in a low-k material. The experimental setup comprised a SEM (FEI XL30) equipped with four nanomanipulators, a parameter analyzer (Keithley 4200-SCS) and an EBIC/RCI amplifier (Kleindiek Nanotechnik). This setup allowed the precise contacting and electrical stressing of individual sub-micrometer size structures to induce in situ dielectric breakdown for RCI imaging [3].
In its most simplistic description, RCI generates a black-white image depending on whether the conductor probed is electrically connected to the current amplifier or not. In this mode, it provides an efficient means of fault site localization in the stressed structures by identifying high-resistance sites characteristic of breakdown.
During the stages of dielectric degradation preceding complete breakdown, the conductor starts showing signs of current collection even when the e-beam is still scanning the adjacent dielectric material. This signal reflects the diffusion of the charge carriers injected in the dielectric close to the conductor and is expected to increase with increasing dielectric degradation. On the other hand, when the e-beam is positioned far away from the connected conductor, one would not expect to detect any current. However, two deviations from this behavior are observed: (i) the RCI image clearly shows the complete parallel line structure implying that current is collected on one conductor even if the beam is hitting another conductor, (ii) when the e-beam is hitting the conductor itself, the RCI contrast is not homogeneous but reflects enhanced current close to the area showing initial trends of dielectric degradation. In this work, we will discuss these mechanisms as they affect the RCI image formation in dielectric breakdown studies.
[1] C.A. Smith et al., IEEE Transaction on Electron Devices ED-33(1986)282
[2] E.I. Cole, Mat. Res. Soc. Symp. Proc 716(2002)B13.1.1
[3] T. Nokuo and H. Furuya, Electronic Device Failure Analysis 2(2009)16
9:00 PM - F8.15
Remote Plasma Processes for Cleaning ILD and CMP Cu Surfaces.
Xin Liu 1 , Fu Tang 1 , Sean King 2 , Robert Nemanich 1
1 Department of Physics, Arizona State University, Tempe, Arizona, United States, 2 Portland Technology Development, Intel Corporation, Hillsboro, Oregon, United States
Show AbstractThe electromigration mechanism in Cu interconnect structures is mainly determined by diffusion along the dielectric cap / copper interface. Various plasma and gas treatments of the Cu surface have been utilized to improve the quality and performance of the interface. However, the low-k dielectrics implemented as an interlayer dielectric (ILD) in Cu interconnects are susceptible to plasma damage. In this work, we have employed remote plasma processes for cleaning both ILD and Cu surfaces after chemical mechanical polishing (CMP). The surfaces were characterized in situ using in situ x-ray photoelectron spectroscopy (XPS), and the bulk effects were monitored with ex situ Fourier transform infrared (FTIR). Low-k dielectrics characterized as high carbon, low porosity (HCLP) and low carbon, high porosity (LCHP). Remote oxygen, hydrogen, nitrogen and hydrogen/nitrogen mixtures were employed. For the HCLP the surface atomic fraction changes insignificantly after a 5 minute plasma treatment of N2 and H2 (4:1) mixture, while more significant changes were observed for pure O2, N2 or H2 plasma treatments. The ex situ Fourier transform infrared (FTIR) also showed a minimized reduction of - CH3 structures, which was consistent with the XPS analysis. We argue that in a mixed plasma, the H-radicals activate the surface and facilitate the formation of a densified surface nitride which retards further etching by H radicals. However, the LCHP ILD demonstrated a reduced resistance to plasma damage. The XPS and FTIR both indicated changes in the elemental composition and the bonding structure under plasma treatments. In addition, the same H-plasma conditions resulted in the removal of the Cu oxide on the CMP surface while residual C and N remained on the surface.
9:00 PM - F8.16
Room Temperature 1.6 μm Photoluminescence and Electroluminescence From in-situ Doped n-type epi-Ge on Si.
Szu-Lin Cheng 1 , Jesse Lu 2 , Gary Shambat 2 , Hyun-Yong Yu 2 , Krishna Saraswat 2 , Jelena Vuckovic 2 , Yoshio Nishi 2 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractA silicon (Si) compatible laser for applications in high speed networks of telecommunication and optical interconnect systems has been an important research topic for several years now but has yet to be practically demonstrated. Recently, highly-doped n-type germanium (Ge) has been proposed to be a strong candidate. The small difference of 0.134 eV between the direct and indirect band gaps of Ge suggests the possibility of a direct band gap transition. Through high concentration n-type doping, the Fermi energy of Ge will be above the indirect conduction band (L valley) edge and the probability that electrons occupy the Ge direct Γ valley will increase. This band filling effect can thus enhance the light emitting efficiency of Ge by raising the possibility of direct transitions.In this work, light emission of highly-doped n-type epi-Ge on Si was studied for the application of Si compatible light sources. In-situ doping technique with PH3 during the epi-Ge growth was applied to achieve high n-type doping concentrations. The highest doping concentration is 1E19 cm-3 with 100% activation, confirmed by SIMS and SRP. The direct band gap emission at 1.6 μm from epi-Ge was observed by photoluminescence (PL) measurements. The direct emission of Ge increases with higher doping concentration, which confirms that the Ge emission efficiency from direct band gap can be improved by band filling of electrons to in-direct L valleys. The highest luminescence enhancement is 15X higher than undoped Ge.Finally, a Ge n+/p light emitting diode (LED) on a Si substrate was made by in-situ doping to study the electroluminescence (EL) properties from highly-doped n-type Ge. Room temperature 1.6 μm EL was obtained from this Ge LED. Unlike ordinary electrically pumped devices, this device shows a superlinear luminescence enhancement at high current. Thermal enhancement effects observed in temperature dependent EL spectra show the capability of this device to operate at room temperature or above. These detailed studies show that Ge can be a good candidate for a Si compatible light emitting device.
9:00 PM - F8.17
A Study of Organic Thin Film Transistors Based on Printing Methods.
Jung-Min Kim 1 , Dong-Hoon Lee 1 , Yong-Sang Kim 1 2
1 Nano Science & Engineering, Myongji University, Yongin, Gyeonggi-Do, Korea (the Republic of), 2 Electrical Engineering, Myongji University, Yongin, Gyeonggi-Do, Korea (the Republic of)
Show AbstractOrganic thin-film transistors (OTFTs) have the key advantage of relatively simple and low temperature processing, low-cost and mechanical flexibility that are useful in many applications, such as active-matrix displays, RFID tags and flexible microelectronics. Several different organic semiconductors have been investigated for the application of TFTs. Among the various organic semiconductors, pentacene-based TFTs are actively investigated for their excellent electrical performance. These OTFTs manufacturing techniques include photolithography, physical vapor deposition (PVD), chemical vapor deposition (CVD) and wet/dry etching. Particularly in the context of low-cost and high throughput, there is a need to demonstrate that inexpensive material deposition and patterning processes. In this reason, we have fabricated pentacene TFTs and circuits with ink-jet and screen printed electrodes. As plastic substrates, polyethersulfone (PES) films were used. The silver ink is used for gate, source and source/drain electrodes by ink-jet and screen printing. The gate insulator, Poly(4-vinylphenol) (PVP) was deposited over the gate electrode to a thickness of 480 nm by spin coating and baked at 200 °C for 1 hour. The PVP solution is prepared by dissolving PVP (10 wt% of solvent) and methylated poly(melamine-co-formaldehyde) (5 wt% of solvent) as a cross-linking agent in propylene glycol methylether acetate as a solvent. Pentacene (Aldrich 97%), without further purification, was deposited at 85 °C on PVP by thermal evaporation with a rate of 0.1 Å/s in a high-vacuum system with a base pressure of 5x10-6 torr. It was deposited as patterned with a shadow mask during thermal evaporation and its thickness was about 70 nm. To evaluate the dynamic performance of pentacene OTFTs with ink-jet and screen printed electrodes, we have fabricated pentacene OTFT circuits. In this work, pentacene TFTs with ink-jet and screen printed electrodes are successfully demonstrated by simple process on the plastic substrate and their electrical properties are compared with conventional methods.
9:00 PM - F8.18
Fabrication Scheme of a High Resolution and High Aspect Ratio UV-Nanoimprint Mold.
Kipil Lim 1 2 , Jung-Sub Wi 1 , Sung-Wook Nam 1 , Soo-Yeon Park 3 , Jae-Jong Lee 3 , Ki-Bum Kim 1
1 Material Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Nano-Materials Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of), 3 , Korea Institute of Machinery and Materials, Daejeon Korea (the Republic of)
Show AbstractNanoimprint lithography (NIL) is considered one of the most economically viable ways to fabricate fine patterns, partially replacing the conventional photolithography process. UV-nanoimprint lithography (UV-NIL) is one type of NIL process that uses UV light to cross-link an NIL resist, which is attracting attention because of its several advantages compared to the NIL process. Fabrication of the UV-NIL mold with high resolution and high aspect ratio pattern is required, among several important issues in UV-NIL process.We propose a new scheme of fabricating a nanoimprint mold for UV-NIL with both a high resolution and a high aspect ratio by employing HSQ and an intermediate α-Si layer on the SiO2/ITO/quartz substrate. From the e-beam lithography process, we obtained line patterns of 40 nm width and dot patterns of 25 nm diameter on the HSQ. We successfully transferred the HSQ pattern to the α-Si layer using the high etch selectivity between the HSQ and the α-Si in Cl2 reactive ion etching process. As a result, we obtained line patterns with a height of 140 nm, and dot patterns with a height of 125 nm. The line and dot patterns had aspect ratios of 3.5:1 and 5:1, respectively. The results of the UV-NIL process shows that patterns from the UV-NIL mold were well replicated to the UV-NIL resist. By introducing an α-Si layer, which has etch selectivity superior to HSQ but has not been prominently used in this process due to its inferior UV transparency, a UV-NIL mold with high resolution and high aspect ratio patterns could be obtained while also minimizing critical dimension loss. We also showed that α-Si patterns themselves do not cause any issues for the UV-NIL process, either theoretically and experimentally.
9:00 PM - F8.19
Novel Test Methods for Adhesion and Micro-abrasion of Conductive Coatings.
Yong-Nam Kim 1 , Jun-Kwang Song 1 , Tae-Min Noh 2 , Hee-Soo Lee 2
1 Material testing center, Korea Testing Laboratory, Seoul Korea (the Republic of), 2 School of Materials Science & Engineering, Pusan National University, Busan Korea (the Republic of)
Show AbstractConductive coatings such as metals, transparent conducting oxides, conducting polymers are thick or thin films which have low electrical resistivity. They have many applications such as electrodes in electrical and electronic devices, EMI shielding, antistatic coatings, display devices, touch panel, and so on. As the application field of conductive coatings has expanded, their mechanical property and durability have become important. Improved mechanical property and durability of conductive coatings ensure long lifetime and high reliability.The relationship between a few of mechanical properties and physical properties of conductive coatings, such as hardness and flexibility, has been studied and are known. However, the adhesion and micro-abrasion of conductive coatings on substrates are less studied. Because conductive coatings which have good adhesion to substrate and high durability against abrasion show superior electrical properties, long lifetime and high reliability, it is needed to measure and analyze their accurate adhesion and wear resistance. Adhesion of coatings is generally tested using a cross-cut tape method or a tensile pull-off method. However, in the cross-cut tape method, coatings with high adhesion cannot be removed from substrates by pulling sticky tape and therefore, coatings with high adhesion cannot be quantitatively analyzed. In the tensile pull-off method, tensile load is applied between coatings and substrates by pulling wires bonded to coatings. If breakage occurs between coatings and substrates, the accurate adhesive strength can be obtained. However, breakages frequently occur not between coatings and substrates but between coatings and wires.In order to study the quantitative adhesion of coatings, a novel scratch method has been developed. In the scratch method, constant or increasing normal load is applied to coatings by a stylus. When coatings are broken by scratch, in general, friction coefficient is varied or acoustic emission signal is generated. However, although ductile conductive coatings are broken during scratch, the variation in friction coefficient and acoustic emission signal are not generated. Therefore, it is necessary to develop the test methods for adhesion and micro-abrasion of conductive coatings.In this study, novel test methods for adhesion and micro-abrasion of conductive coatings such as metal, conducting oxide and conducting polymer were investigated. While conductive coatings were scratched with stylus and abraded with ball under micro load, the variation in resistivity of conductive coatings was measured and recorded. As conductive coatings were broken by scratch or abrasion, their resistivity was varied. Therefore, from the variation in resistivity, the accurate adhesion and wear resistance could be analyzed.
9:00 PM - F8.2
Direct Measurement of Hot-spot Temperature in Flip-chip Solder Joints With Cu Columns Under Current Stressing using Infrared Microscopy.
You Chun Liang 1 , Chih Chen 1
1 Department of Materials Science and Engineering, National Chiao Tung University, Hsin-Chu Taiwan
Show AbstractAs the required performance in microelectronic devices becomes higher, the flip-chip technology has been adopted for high-density packaging. Furthermore, to meet the miniaturization trend of portable devices, the dimensions of the solder bumps continue to shrink, causing the current density in each solder joint to increase abruptly. Therefore, electromigration in the solder bumps has become an important issue. Several studies reported that a hot spot exists in flip-chip solder bumps accelerating electromigration, and the hot-spot temperature in the solder bump decreases for the solder joints with a thicker under-bump-metallization (UBM). The Cu column is a thick UBM structure developed to alleviate current crowding in a flip-chip solder joint under operating conditions. Yet, there are no experimental data to verify that whether the hot-spot temperature is also decreased in the solder bumps with Cu columns. In this paper, the temperature distribution during electromigration in Cu column flip-chip solder joints is directly inspected using infrared microscopy. It is found that the temperature in the solder becomes relatively uniform during current stressing. Thus, it is an excellent structure to relieve current crowding effect and local Joule heating effect in solder. In addition, the correlation between electromigration failure and the temperature distribution will be discussed.
9:00 PM - F8.20
Tracking Grains Behaviour During in-situ Electromigration Within 100nm Copper Lines by Synchrotron X-ray Diffraction.
Pierre Bleuet 1 , Patrice Gergaud 3 , Patrick Lamontagne 2 , Lucile Arnaud 3 , Jean-Sebastien Micha 1 , Xavier Biquard 1 , Olivier Ulrich 1 , Francois Rieutord 1
1 , CEA, INAC, Grenoble France, 3 , CEA, LETI, MINATEC, Grenoble France, 2 , ST Microelectronics, Crolles France
Show AbstractWith the decrease of the transverse size of copper lines, current densities are getting so high that physical transportation of matter arises that leads to defects or even failures of electronic devices. Here, we propose to study this so-called electromigration using synchrotron x-ray microdiffraction that allows tracking crystalline phases, identifying grain distriutino and grain orientation, and even getting local strain and stress, ultimately down to the probe size.Experiments have been carried out at the European Synchrotron Radiation Facility BM32, on sample provided by ST Microelectronics. During these experiments, 100nm copper lines, of variable lengths, have been submitted to high current densities and high temperature to make the electromigration test compatible with a synchrotron experiments. All along the electromigration process, polychromatic microdiffraction patterns have been acquired across and along the lines. Given the probe size (about 1 micrometer) with respect to the line cross section, the signal to noise ratio onto the CCD detector is rather poor. However, a rigid motion of diffraction spots during the electromigration has been identified, that corresponds to grains rotation over themselves. This unprecedented observation on such small lines is, however, compatible with other studies on coarser lines but anyway small than a micrometer. Experimental details and constraints will be given. Grain rotation will be quantified along the line, together with SEM observations.
9:00 PM - F8.21
Ex-situ TSV Characterization by Synchrotron X-ray Nanoradiography.
Pierre Bleuet 1 , Assous Myriam 2 , Peter Cloetens 3 , Patrick Leduc 2 , Patrice Gergaud 2 , Aurelie Thuaire 2 , Remi Tucoulou 3
1 , CEA, INAC, Grenoble France, 2 , CEA, LETI, MINATEC, Grenoble France, 3 , European Synchrotron Radiation Facility, Grenoble France
Show AbstractThree-dimensional integration is now considered as a key alternative for high volume and low cost applications. It is to a large extent based on Through-Si Via (TSV). This work deals with 3D ICs with high density of 3D interconnects, of up to 104 via/mm2. Micrometer or even sub-micrometer TSVs are required to reach such densities.Most direct imaging methods for void visualization and detection are not compatible with statistical analyses. Electrical measurements can give copper filling quality but gives neither morphological data nor precise voids location and numbering. SEM can be used for that purpose. However, electrons do not have sufficient penetration depth and FIB-SEM must be used, preventing from statistical analysis and deep understanding of via formation mechanisms. To overcome these issues, we propose to use x-ray imaging that can give, in a single shot, nanoradiographs of tens of TSVs that can then be post-processed and analysed for void detection.To get x-ray radiographs compatible with TSVs dimensions, it is mandatory to use an imaging technique with the highest resolution possible, i.e. with the smallest pixel size achievable. To get a reasonable photon statistics per pixel, 3rd generation synchrotron radiation must be used, that are the most brilliant x-ray sources available today. Coupled with the recently developed high efficiency focusing optics, sub-100nm resolution radiographs can be obtained on a field of view of about 100 micrometers. An experiment has been performed at the European Synchrotron Radiation Facility beamline ID22NI, where centimetre samples containing hundreds of TSVs have been mapped out using x-ray radiography. Ex-situ results will be shown, i.e. with different annealing conditions, filling and deposition processes, for copper TSV with diameters ranging between 1 to 5 micrometers. The method will be detailed and assessed together with its limitations.
9:00 PM - F8.22
Micromechanics and Damage Processes in Complex Multi-Layer Die Structures.
Alexander Hsing 1 , Andrew Kearney 2 , Reinhold Dauskardt 1
1 Materals Science and Engineering, Stanford University, Stanford, California, United States, 2 , Cisco Systems, San Jose, California, United States
Show AbstractAdvanced semiconductor technology nodes require the integration of heterogeneous multilayer thin-film structures with vastly different mechanical properties, complex residual stresses, and fragile dielectric materials. In the case of 3-D structures, significantly increased mechanical constraint and local stresses present further challenges. Quantitative characterization techniques and an understanding the mechanical behavior of the overall multilayer stack structure are of critical importance but currently lacking. We demonstrate measurements using a novel micro-probe test metrology based on a micron-scale diameter stiff probe to directly measure a range of mechanical properties of multilayer thin-film device structures. Tensile, compressive and cyclic loading capabilities coupled with precise temperature control allow for the replication of various stresses experienced by different multilayer materials under a wide range of real-world conditions. This metrology system measures properties at the relatively unexplored length scale between the nanoscale, where loads are too low and compliance is too high, and conventional mechanical testing where loads are too high. Salient mechanical properties like stack compliance, strength characteristics, fracture behavior, and fatigue resistance are probed. This allows characterization of critical stress levels required to initiate delamination under a die bump. Measured mechanical properties can be correlated to design parameters like material density, line aspect ratio, and film thicknesses, etc. The metrology system can also be used to characterize yield and hardening properties of different solder compositions, as well as the dependence of these mechanical properties on the solder ball cooling rate after reflow. In addition, the temperature dependence of the mechanical properties and failure criteria of back-end interconnect stack structures will be discussed. The dependence of stresses developed within interconnect structures on pad size, pad design and bump geometry will be addressed. A technique for micron-scale soldering of the microprobe tip to die features or directly onto solder balls on the die backside enables precise and highly localized tensile loading of underlying multilayer interconnect structures. Deformation, defect evolution and ultimate failure mechanisms due to localized tensile stress will also be discussed.
9:00 PM - F8.3
Stacking Sequence Effect on the Electrical and Optical Properties of Multi-staked Flexible IZO-Ag-IZO Electrodes for Flexible Organic Photovoltaic.
Yong-Seok Park 1 , Han-Ki Kim 1
1 Display Materials Engineering, khung hee university, Su-won Korea (the Republic of)
Show AbstractWe investigated the stacking sequence effect of indium zinc oxide (IZO)-Ag and IZO-Ag-IZO on the characteristics of multi-stacked flexible transparent electrode for organic photovoltaics. In spite of the similar sheet resistance of IZO-Ag stacked electrode to IZO-Ag-IZO stacked electrode, the optical transparency of the IZO-Ag-IZO stacked electrode is much higher than that of the IZO-Ag stacked electrode at the wavelength region of 400-800 nm due to effective antireflection in the symmetric oxide-Ag-oxide structure. Furthermore, the flexible organic solar cells (OSCs) fabricated on the IZO-Ag-IZO stacked multilayer electrode showed higher power conversion efficiency than the flexible OSC fabricated on the IZO-Ag stacked multilayer electrode due to the higher optical transparency of the IZO-Ag-IZO stacked multilayer electrode in the main absorption region of poly(3-hexylthiophere) and 1-(3-methoxycarbonyl)-propyl-1-phenyl-(6,6) C61 layer. This indicates that the multi-stacked electrode with IZO-Ag-IZO sequence is more beneficial than IZO-Ag sequence for low resistance and high transparent electrode in flexible OSCs.
9:00 PM - F8.4
Electrical, Optical, Structural Properties of Nb:TiO2 and Nb:Ti2O3/Ag/Nb:Ti2O3 Multilayer Electrode as a New Transparent Conducting Oxide for Optoelectronics.
Jun-Hyuk Park 1 , Han-Ki Kim 1
1 Display Materials Engineering, Kyung Hee University, Yongin-Si Korea (the Republic of)
Show AbstractWe have investigated the electrical, optical, structural properties of Nb-doped Ti2O3 electrode grown by conventional DC/RF magnetron sputtering system as a new transparent conducting oxide for organic photovoltaics and OLEDs. Also, we fabricated the multilayer structure, which introduce the metal layer between the oxide layer, such as Nb:Ti2O3/Ag/Nb:Ti2O3 multilayer electrode to compare the property with single Nb:Ti2O3 layer. The Nb:Ti2O3 electrodes prepared at room temperature have high electrical resistivity and low optical transparency. However, we could obtain the Nb:Ti2O3 electrode with low sheet resistance of ~100 ohm/square and high optical transparency by rapid thermal annealing under the vacuum atmosphere. It was found that NTO electrodes are critically dependant on the oxygen, and temperature. On the other hands, in the case of the Nb:Ti2O3/Ag/Nb:Ti2O3 multilayer electrode, in spite of preparing at room temperature without heat treatment, it was shown that the electrical and optical properties of the Nb:Ti2O3/Ag/TNb:Ti2O3 multilayer electrodes could be improved by the insertion of an Ag layer with optimized thickness between oxide layers, due to the antireflection effect. We were able to obtain the Nb:Ti2O3/Ag/ Nb:Ti2O3 multilayer electrode with very low sheet resistance of 2~9 ohm/square, high optical transparency of ~87% in the visible region. Nb:Ti2O3 and Nb:Ti2O3/Ag/Nb:Ti2O3 multilayer electrode as a new transparent conducting oxide are promising materials to alternative to commercial ITO.
9:00 PM - F8.5
The Dominant Ionization Processes in an rf Reactive Magnetron Plasma.
Marites Violanda 1 2 , Henrik Rudolph 1 2 , Frans Habraken 2 , Alberto Palmero 3
1 Nanophotonics Section, Debye Institute for NanoMaterials Science, Department of Physics and Astronomy, Utrecht University, Utrecht Netherlands, 2 Surfaces, Interfaces and Devices, Department of Physics and Astronomy, Faculty of Science, Utrecht University, Utrecht Netherlands, 3 Instituto de Ciencia de Materiales de Sevilla, Universidad de Sevilla, Sevilla Spain
Show AbstractRecent rf reactive sputtering magnetron deposition experiments with silicon sub-oxides [1] have shown a surprisingly large flux of SiO+ ions arriving at the deposition surface. The flux of SiO+ ions is larger than the corresponding O+ ion flux at lower oxygen partial pressures. This strong presence of SiO+ in the plasma is somewhat surprising, but it could be a consequence of a much larger ionization cross section for SiO compared to other species present in the plasma volume. In this work we investigate the various possible SiO ionization mechanisms: photoionization, electron impact ionization and Penning Ionization, based on first principle methods, and determine the absolute cross section for the various processes. Based on estimations of the plasma densities and properties it is possible to determine which process is the dominant cause of the ions and where in the plasma volume the ions are created. With a simple model of the distribution of the various species in the plasma volume, and the electromagnetic fields present, we are able to qualitatively describe the resulting angular distribution of the ions arriving at the deposition surface.[1] Distinct processes in radio-frequency reactive magnetron plasma sputter deposition of silicon sub-oxide films, E. D. van Hattum, A. Palmero, W.M. Arnoldbik, H. Rudolph and F.H.P.M. Habraken. Journal of Applied Physics 102, art. No. 124505 (2007).
9:00 PM - F8.6
Wafer Bonding for Backside Illuminated CMOS Image Sensors Fabrication.
Viorel Dragoi 1 , Gerald Mittendorfer 1 , Alexander Filbert 1 , Markus Wimplinger 1
1 , EV Group, ST. Florian/Inn Austria
Show AbstractOne important application based on MEMS technology and 3D integration techniques is the backside illuminated CMOS image sensor: In order to overcome the pixel area limitation by the metal interconnects in CMOS image sensor the backside of the image sensor has to be “open” for the light after fully processing the sensor wafer.One of the most used process flows consists of:- Sensors fabrication in CMOS technology- CMOS wafer bonding to a blank Si wafer (usually named handle or carrier)- Back-thin CMOS wafer (typically by grinding and etching or polishing)- Fabricate the camera objective (add colour filters, lenses, etc.)Two wafer bonding processes are competing for this application: low temperature direct bonding and adhesive wafer bonding using polymer layers.In the direct bonding process, the CMOS wafer has to be first planarized (flat surface) in order to meet the requirements of fusion bonding. In order to obtain the flat surface for bonding, the CMOS wafer is first planarized using silicon oxide deposition (e.g. PECVD) and oxide layer polishing using a standard Chemical Mechanical Polishing (CMP) process.After CMOS planarization the wafers are plasma activated and aligned using either edge-to-edge alignment (maximum accuracy: ±50 µm) or optical alignment (maximum accuracy: <1 µm). Wafers are typically brought into contact at room temperature for spontaneous bonding and then thermally annealed at temperatures of 200°C - 400°C.After the wafer bonding step the initial CMOS substrate is back-thinned using grinding and etching, then the entire sensor structure is completed by specific steps (e.g. adding color filters).In adhesive wafer bonding process flow the planarization of CMOS wafer is accomplished by the polymer bonding layer. It is known that polymer materials can fill gaps, compensate flatness variations and even incorporate particles with diameters in the range of polymer layer thickness. The process flow is simplified in this case compared to plasma activated bonding approach by replacing oxide planarization with a polymer spin- or spray-coating process.In the end, after bonding and CMOS substrate removal, the final camera structure fabrication at wafer level is completed by adding the optical elements (lenses, filters, spacers between optical elements). This part of the process can be also completed by wafer bonding processes: in this case the process of choice is typically adhesive wafer bonding based on UV-curable polymers. This process is very effective and is a room temperature process which minimized the risk of adding stress to the already built multi-layered structure.The present paper reports on the specific process flows of the two wafer bonding techniques by examples of technical solutions (processes, materials) and solutions to fulfil the strict requirements raised by this application.
9:00 PM - F8.7
Mechanical and Electrical Properties of Electroplated Copper Thin Films Used for Thin Film Interconnection.
Murata Naokazu 1 , Miura Hideo 1 , Suzuki Ken 1 , Tamakawa Kinji 1
1 Fracture and Reliability Research Institute, Tohoku University, Semdai, Miyagi, Japan
Show AbstractMechanical and electrical properties of electroplated copper films were discussed experimentally considering the change of their micro texture caused by heat treatment. Both the static and fatigue strength of the film changed drastically and there were two fatigue fracture modes in the films. One was a typical ductile intragranular fracture mode and the other was brittle intergranular one. The reason for the variation of the strength of the electroplated copper thin films was attributed to the variation of the average grain size and the characteristics of grain boundaries. In addition, The electrical reliability of the electroplated copper interconnections was discussed under electromigration tests. Though abrupt fracture mode due to the local fusion appeared in the as-electroplated films, the life of the interconnections was improved significantly after the annealing at 400oC. Typical change of the surface morphology of the film, i.e., the formation of voids and hillocks were observed on their surfaces. This reason is that the micro texture that consisted of fine grains and porous grain boundaries changed to texture that consisted of coarsening grains. However, the stress migration occurred in the interconnection with annealing at 400 oC for 3 hours. In addition, the hillocks were easier to form on the interconnection whose width was narrow. This reason is that high tensile residual stress occurred when micro-texture change from porous to dense by annealing, and the interface constraint was larger as its width was narrower. These results clearly indicated that micro-texture that consisted of fine grains and porous grain boundaries deteriorated reliabilities of thin film interconnections.
9:00 PM - F8.8
Fabrication and Electrical Properties of PEDOT Coated PVDF Nanowebs.
Sun Yoon 1 , Dipankar Mandal 1 , Kap Jin Kim 1
1 Advanced Polymer and Fiber Materials, Kyung Hee University, Yongin-si, Gyeonggi-do, Korea (the Republic of)
Show Abstract Much attention has been paid on the research and manufacture of conducting polymers to use in organic electronic devices. The typical fabrication method is spin coating or inkjet printing, especially for making conducting thin film. But these preparation methods are not sufficient enough for many electronic devices(sensors for gas, tactile, and moisture detection, EMI shields, light electric signal transmitting devices, etc.) that need more surface-to-volume ratio and sometimes in bulk form. Thus, in this work, we have adopted a novel method, namely electrospinning followed by vapor phase polymerization(VPP) of 3,4-ethylenedioxyyhiophene(EDOT). By this method we can fabricate poly(3,4-ethylenedioxyyhiophene)(PEDOT) coated poly(vinylidene fluoride)(PVDF) nanofiber webs having high surface-to-volume ratio and enhanced conductivity.We have prepared conductive nanofiber webs(CNWs) by electrospinning the N,N-dimethylacetamide(DMAc)/acetone (6/4 v/v) solution of PVDF/FeCl3 and afterwards we performed VPP of EDOT on electrospun nanofibers.Here, FeCl3 was used as an oxidant for polymerization of EDOT. To get desired conductivity we have optimized various processing parameters, i.e., oxidant concentrations, and polymerization duration. From scanning electron microscopy, the diameters of PEDOT-coated PVDF nanofiber were observed to be in the range of 230 nm to 500 nm and PEDOT was found to be coated on the surface of the nanofiber. The content of PEDOT polymerized on PVDF nanofibers could be monitored as a function of vapor phase polymerization time using FT-IR spectrum. The conductivity was evaluated from current-voltage(I-V) curve.Furthermore, we could improve the conductivity of the above CNWs by one order of magnitude by spraying chemically-modified multiwall carbon nanotube simultaneously during electrospinning process and then applying mechanical pressure(squeezing) to the electrospun nanofiber webs before VPP of EDOT. To check the feasibility of applying these CNWs to electrode for PVDF-nanofiber web based piezoelectric sensor, gas sensor, temperature sensor, etc, we have measured piezoelectric signal with periodic pressure, changes in conductivity with HCl and NH3 vapor concentrations, and change in resistance with temperature. And we also tested its EMI shielding ability. More details will be discussed in the presentation.Acknowledgement : This work was supported by the Korea Science and Engineering Foundation(KOSEF) grant funded by the Korea government(MEST)(R11-2005-065) and Industrial Source Technology Development Programs(funded by the Ministry of Knowledge Economy(MKE, Korea)).
9:00 PM - F8.9
Nanoscale Ruthenium Coatings of MEMS Switches Contacts.
Sergey Karabanov 1 , Andrey Karabanov 2 , Dmitriy Suvorov 1 , Benoit Grappe 3 , Caroline Coutier 3 , Henri Sibuet 4 , Boris Sazhin 1 , Anatoliy Krutilin 1
1 , Ryasan Metal Ceramics Instrumentation Plant JSC, Ryazan Russian Federation, 2 , Solar Energy Ltd., Ryazan Russian Federation, 3 , Schneider Electric Industries , Grenoble France, 4 , CEA-Leti , Grenoble France
Show AbstractThe paper reports the tests results of ruthenium contacts coatings of magnetically controlled MEMS switches. During the tests the contact resistance was measured and the lifetime of MEMS switches was evaluated. After testing the analysis of the form and contact surface structure using SEM-method was carried out. The experiment results showed that the application of ruthenium nanolayers as the contact coating at slight increase of the contact resistance improves the lifetime of MEMS switches considerably.Nowadays the increase of the lifetime of all MEMS switch types (RF MEMS relays, magnetically controlled on-off MEMS switches) is the most actual problem.The work resource and operating characteristics, first of all, contact resistance, of any switching unit, the basis of the construction of which is a dry contact, are determined by the contact coating properties. This is true for MEMS switches too.The paper presents the results of the study of the operating characteristics of magnetically controlled MEMS switches with ruthenium and gold contact coatings of up to 100 nm thickness.During tests the following switching mode was used: switching voltage – 3 V, current - 10 µA. Each MEMS switch was subjected to 100 million cycles switching at the frequency of 100 Hz. After testing the contact surface investigation by SEM-method and electrical characteristics measurement was carried out. The paper presents SEM-images of the contacts surface and statistical date of electrical characteristics.After 100 million switching cycles MEMS switches with nanoscale ruthenium coating have shown 100% operating capacity; 16% of switches with gold contacts turned out to be inoperative due to electrical contacts sticking. The results of researches by SEM-method show that the contacts without nanoscale coating have the traces of strong erosion and melting; the contacts with nanoscale ruthenium coating practically did not change the form and flatness.So, the test results indicate that nanoscale ruthenium coatings of the electrical contacts provide excellent resource for the switches operation of hundred millions and more cycles.
Symposium Organizers
Alshakim Nelson IBM Almaden Research Center
Azad Naeemi Georgia Institute of Technology
Hyungjun Kim Yonsei University
Hyun Wook Ro National Institute of Standards and Technology
Dorel Toma TELUS Technology Development Center
F9: 3D Integration/TSV/Packaging
Session Chairs
Thursday AM, April 08, 2010
Room 2010 (Moscone West)
9:45 AM - **F9.1
3D CMOS and MEMS Integration Using Mechanically Flexible Interconnects and Novel Through Silicon Vias.
Muhannad Bakir 1 , Hyung Suk Yang 1
1 , Georgia Tech, Atlanta, Georgia, United States
Show Abstract3D (vertical) integration provides the best of hybrid integration and monolithic integration of CMOS and MEMS; it allows independent fabrication of CMOS and MEMS, while providing the high performance electrical connection resulting from shortened interconnection length. Moreover, using conventional approaches to interconnection have been known to induce high levels of stress, causing die warpage which in turn can change the performance of MEMS devices. The paper presented will describe a new 3D integration strategy that addresses above issues using two novel interconnect technologies; mechanically flexible interconnects (MFI) and Through Silicon Vias (TSV). Collectively, these interconnect technologies enable 3D integration of a state-of-the-art CMOS process with an arbitrary MEMS process.A novel MFI technology with up to 25um of vertical gap is developed and demonstrated. With its high in-plane compliance, the need for underfill is eliminated thereby making the wafer level integration easier to achieve. With its high vertical range-of-motion (ROM) and out-of-plane compliance, deflection caused by the CTE mismatch is relieved and at the same time, provides compensation for non-planar wafer surfaces during the assembly process.MFIs are batch fabricated by photo-lithographically patterning an electroplating mold on a curved surface, which is created by reflowing a photo-defined sacrificial polymer structure. The resulting lead has a smooth vertical profile that minimizes the concentration of stress thereby increasing the vertical range in which the lead can deflect without breaking. Mechanical finite element simulations and measurements were also performed showing that varying geometrical parameter can yield out-of-plane compliance as high as 25mm/N. In order to integrate MEMS devices, TSVs are essential; in order to expose MEMS to the environment for sensing, one needs capability for back-to-front assembly. Unfortunately, many novel TSV technologies exploit the fact that CMOS ICs are thinned, making them unsuitable for many MEMS applications (e.g. devices w/ deep trenches). Therefore, a novel high-aspect-ratio TSV technology that can be fabricated on thick wafers has been developed. In this paper, a seed layer fabrication technique using a mesh dielectric layer is demonstrated, which enables forming of a seed layer quickly independent of via hole diameter and depth. Also, through the use of a bi-metal seed layer, a CMP-free planarization on one side of the wafer is demonstrated, potentially enabling the fabrication of TSVs after sensitive MEMS devices have been fabricated first on the same wafer.
10:15 AM - F9.2
Interfacial Delamination of Through Silicon Vias in 3-D Interconnects.
Suk Kyu Ryu 1 , Kuan Lu 2 , Qiu Zhao 2 , Xuefeng Zhang 2 , Jay Im 2 , Paul Ho 2 , Rui Huang 1
1 Department of Aerospace Engineering and Engineering Mechanics, University of Texas at Austin, Austin, Texas, United States, 2 Microelectronics Research Center, University of Texas at Austin, Austin, Texas, United States
Show AbstractThe incorporation of through silicon vias (TSVs) poses a significant challenge to thermo-mechanical reliability of the 3-D interconnects. In particular, the mismatch in coefficients of thermal expansion (CTEs) between the conducting metal in TSV and the silicon matrix can generate thermal stresses sufficient to degrade the performance of stress-sensitive devices and to cause cohesive cracking of Si or interfacial delamination. In this study, we investigated the mechanics of interfacial delamination for TSVs. First, the near-surface fields of thermal stresses were analyzed for a simplified copper TSV structure. Based on a semi-analytic solution, the delamination under a positive thermal load corresponding to heating is mainly driven by the shear stress near the wafer surface, i.e. a mode II fracture. On the other hand, the delamination under a negative thermal load corresponding to cooling is driven by both the shear stress and the positive radial stress, i.e. a mix-mode fracture. The energy release rate (ERR) that drives the TSV delamination was then calculated as a function of the delamination crack length by the finite element method. It is found that the ERR increases with the length of the crack and approaches a steady-state solution, which is proportional to the diameter of TSV and scales with the square of the thermal load. For Cu TSVs, the ERR can exceed 10 J/m2 for a via diameter greater than 20 µm. Several other metals are considered as alternative TSV materials. The crack driving force can be significantly reduced by using low CTE materials such as W and Ni. Finally, numerical simulations are developed to study the initiation and growth of interfacial delamination cracks as well as the associated via pumping phenomenon, based on a nonlinear cohesive interface model.
10:30 AM - F9.3
Carbon Rich a-SiC:H as Dielectric Barrier for Interconnections and TSV Insulation.
Cedric Charles-Alfred 2 , Guillaume Gerbaud 3 , Jean-Paul Barnes 1 , Agnes Granier 4 , Vincent Jousseaume 1
2 , STMicroelectronics, Grenoble France, 3 , CEA-INAC, Grenoble France, 1 , CEA-LETI-MINATEC, Grenoble France, 4 , IMN, Nantes France
Show AbstractAmorphous SiCNH (dielectric constant k=5.2) is used by the microelectronic industry as dielectric barrier in interconnections. However, in order to fit the new performances required for future technological nodes, the dielectric barrier permittivity needs to be reduced. This k reduction should be performed without compromising the ability to block copper diffusion and keeping in mind the other important parameters for its integration (thermal stability, etching selectivity, adhesion). This study deals with the deposition of amorphous hydrogenated silicon carbide (a-SiC:H) as a low-k barrier against copper diffusion. This type of material deposited using trimethylsilane was firstly envisaged as dielectric barrier for the 90 nm node but was rejected for stability concerns [1-2]. More recently, works were performed to introduce a bilayer stack comprising a SiCNH thin adhesion/copper blocking layer and a highly carbonated low k SiCH in order to decrease the dielectric barrier permittivity [3]. However, the use of this type of bilayer induces an increase of the total barrier dielectric constant. Our approach is based on the introduction of carbon in SiCH through the co-deposition of an organic precursor with trimethylsilane using Plasma Enhanced Chemical Vapor Deposition (PECVD). Three organic molecules were compared (toluene, ethylene and propylene) with the aim of investigating the impact of the precursor chemistry on the deposited film properties, especially the dielectric constant and the barrier properties against copper diffusion. Several material characterizations including FTIR, ellipsometry, X-Ray reflectivity, solid-state NMR, SIMS, C(V) were carried out in order to investigate the film properties. For the three precursors studied, soft plasma conditions and low substrate temperature favor carbon incorporation in the SiCH thin films and this carbon incorporation leads to a decrease of the permittivity. Then, the dielectric constant (measured at 100 kHz) can be reduced from 4.8 to 3.1. It is shown that the free volume, supposed to be generated by the incorporation of phenyl rings using toluene, does not seem to impact the reduction of the dielectric constant, compared to the other linear precursors. It is also shown that the incorporation of a high amount of carbon in the film can lead to the formation of carbon clusters which can be detrimental for barrier properties against copper diffusion. A compromise must be done between low k and barrier properties by selecting the proper chemistry and deposition conditions. Finally, first results on the conformality of these different depositions on high aspect ratio through silicon via will be also presented in order to investigate the potentiality of these materials as insulating layers for TSV.[1] M.J. Loboda, Microelec. Eng., 50 (2000) p15. [2] V. Jousseaume et al, Materials Science in Semiconductor processing, 7 (2004) p301.[3] G. Bonilla et al, AMC proceedings, (2009) p673.
10:45 AM - F9.4
Fluxless Bonding Using Vacuum Ultraviolet and Formic Acid for 3D Interconnects.
Katsuyuki Sakuma 1 2 , Naoko Unami 1 , Shuichi Shoji 1 , Jun Mizuno 1
1 , Waseda University, Tokyo Japan, 2 , IBM Research - Tokyo, Kanagawa Japan
Show Abstract Joints with micro-bump interconnections are widely used to connect the electrode pads between integrated circuits (ICs) and substrates. As systems become faster, there are increasing demands for smaller packages and finer-pitched interconnections. At the same time, 3D chip integration where multiple 2D circuits are stacked on top of other 2D circuits and electrically connected by vertical interconnections require smaller fine-pitch micro-bump technologies [1-3]. Conventional solder joints use liquid flux to remove the solid oxide film during the bonding processes. It is necessary to clean the flux residues after the reflow process, since they can cause reliability problems. However as the bump pitch becomes smaller, it becomes more difficult to remove the flux residue. There are growing demands for fluxless soldering and new surface cleaning methods for fine pitch 3D interconnects. We have developed a novel surface treatment process using vacuum ultraviolet (VUV) light with a wavelength of 172 nm and formic acid vapor. The vapor from formic acid (HCOOH) removes the metal oxides from the bonding surface after the VUV treatment and before the bonding. Evaporated Cu/Sn and immersion Au were used for the bonding micro-bumps and bonding pads in our evaluations. Different cleaning conditions with VUV/O3, formic acid vapor, or both were compared and evaluated. X-ray Photoelectron Spectroscopy (XPS) and Scanning Electron Microscopy (SEM) were used to study the surface elemental composition and geometry of the bumps and pad surfaces before and after the cleaning. The photoelectron spectra of C1s, Sn3d, and Au4f were obtained with XPS. The XPS results showed the atomic carbon concentration was significantly decreased by the VUV/O3 and formic acid treatment process, while the Sn and Au concentrations increased because of the removal of organic contaminants and oxidation from the surfaces. The bonding strength of the Cu/Sn bumps was evaluated using a shear test tool. The results shows that the combination of VUV/O3 and formic acid treatment almost doubled the bonding strength compared to the bumps without treatment.References1. J. U. Knickerbocker, et al., Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection, IBM J. Res. & Dev., vol. 49 (4/5), 2005.2. M. Koyanagi, et al., “Future System-on-Silicon LSI chips, “ IEEE MICRO, 18(4), 1998. pp17-223. K. Sakuma, et al., "3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections,” Proceedings of the 57th Electronic Components and Technology Conference (ECTC), 2007, pp. 627-632.
11:30 AM - **F9.5
Impact of 3D Integration on CMOS Transistors.
Patrick Leduc 1 , Maxime Rousseau 2 , Francois De Crecy 1 , Myriam Assous 1 , Aurelie Thuaire 1 , Barbara Charlet 1 , Alexis Farcy 2 , Lea Di Cioccio 1 , David Bouchu 1 , David Henry 1
1 , CEA-Leti, Grenoble France, 2 , STMicroelectronics, Crolles France
Show AbstractThe purpose of the paper is to discuss the influence of 3D integration, including copper through silicon via (TSV), on CMOS devices. Both thermo-mechanical and electrical couplings were considered in this work. In a first part, the impact of thinning process was evaluated. 65nm bulk CMOS wafers were thinned down to 5 µm. Electrical performances of NMOS and PMOS transistors were compared to reference non-thinned wafers. In a second part, the impact of TSV proximity to transistors was studied. Thermo-mechanical and electrical aspects were considered using simulation and electrical characterizations. For these experiments, 65 nm bulk CMOS wafers were stacked on bulk silicon carrier wafers using direct bonding. Their substrate was thinned down to 15 µm. 4µm-large copper TSVs were then process on the wafer backside. Using specific test structures, the impact of TSV on 65nm transistors was measured. The results were compared to simulations.
12:00 PM - F9.6
An Optimized 300mm BCB Wafer Bonding Process for 3D Integration.
Pratibha Singh 1 2 , John Hudnall 2 , Jamal Qureshi 3 2 , Vimal Kumar Kamineni 3 , Chris Taylor 4 2 , Andy Rudack 2 , Alain Diebold 3 , Sitaram Arkalgud 2
1 , GLOBALFOUNDRIES Inc., Albany, New York, United States, 2 , SEMATECH, Albany, New York, United States, 3 , College of Nanoscale Science and Engineering, SUNY, Albany, New York, United States, 4 , Hewlett-Packard Company, Corvallis, Oregon, United States
Show AbstractWafer bonding using BCB has been discussed in the past for 3D integration. This paper reports the development and characterization of a manufacturable BCB bonding process for 300 mm wafers using standard 300 mm tools. A systematic optimization approach has been developed to characterize the bulk properties of the BCB film, that can be applied to various integration schemes. In this paper, we specifically discuss one such application—handle wafer bonding. BCB bonding for a range of cross-linking levels has been investigated. The cross-linking level of BCB before bonding is determined using a IR VASE technique. The impact of BCB film preparation and bonding condition on bond quality is characterized using scanning acoustic microscopy (SAM) , IR microscopy, razor blade test, and four-point bend methods. Based on the results from this characterization, an optimum cross-linking level for BCB film before bonding was determined for 300 mm wafers to obtain void-free and dendrite-free bonds. TSV wafers bonded using the optimized BCB process conditions have successfully sustained backgrinding, dry thinning, and standard BEOL metalization steps.
12:15 PM - F9.7
A Three Dimensional Self-folding Package (SFP) for Electronics.
Jeong-Hyun Cho 1 , Steve Hu 1 , David Gracias 1
1 Department of Chemical and Biomolecular Engineering, Johns Hopkins University, Baltimore, Maryland, United States
Show AbstractWe describe the concept of a 3D self-folding package (SFP) for sensors and electronic devices. The strategy is based on self-assembly strategies developed in our laboratory wherein 2D lithographically patterned panels interconnected with hinges spontaneously assemble when selected panels are released from the substrate. Folding can also be triggered by temperature or selected chemicals. For packaging of electronic devices, panels are lithographically patterned around previously fabricated devices. Subsequent layers of lithography define a set of hinges that interconnect the panels. The final step involves triggering the self-folding. After self-folding the electronic devices are positioned on the surfaces of a hollow polyhedron. The SFP process is very versatile; we describe self-folding of structures with sizes ranging from 100 nm to 2 mm and with a wide range of materials ranging from metals to polymers to ceramics. The process is also highly parallel and packaging can be carried out in a highly parallel and cost-effective manner. Additionally any polyhedral shape can be fabricated and the process can easily be integrated with conventional CMOS fabrication. In addition to advantages of the SFP process, here, we will also discuss challenges such as forming reliable interconnects between the electronic devices on the package and to the outside world.
12:30 PM - F9.8
Material, Process and Geometry Effects on Through-Silicon via Reliability and Isolation.
Aditya Karmarkar 1 , Xiaopeng Xu 2 , Sesh Ramaswami 3 , John Dukovic 3
1 , Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India, 2 , Synopsys, Inc., Mountain View, California, United States, 3 , Applied Materials, Inc., Santa Clara, California, United States
Show AbstractModern electronics requires integrated circuits to be lighter, smaller and to provide high performance with low power dissipation. These requirements call for high densities and heterogeneous integration. Three dimensional (3D) integration using through-silicon via (TSV) provides the requisite integration densities along with the improvement in system performance. However, 3D integration with TSVs forms intricate structures that contain materials with widely varying chemical and mechanical properties. These TSV structures undergo a number of thermal cycles during the fabrication process. Due to the differences in the material properties, mechanical stresses are introduced in the structures. The mechanical stresses have serious implications for the reliability of the TSV structures. High mechanical stress in the TSV and/or the insulating layers may lead to interface de-bonding and cause system failure. Hence, regions of the TSV structure vulnerable to failure must be identified and the fabrication process must be designed to minimize the detrimental effects of mechanical stresses. The stress impact on reliability also depends on the TSV geometry and the strength of the materials used. The materials and geometries must be designed such that they are able to withstand the mechanical stresses under the operating conditions. Additionally, TSV layout and the properties of insulating layers affect the system performance, and may lead to lower speeds and higher power dissipation. Hence, the materials and the geometries must be chosen to optimize the system performance. A thorough assessment of the factors that affect the reliability and isolation performance of TSVs is necessary to improve the design robustness. This study presents an analysis of process-induced mechanical stresses in TSVs and their impact on reliability, as well as the TSV geometry impact on isolation performance. Here, an FEM-based advanced three-dimensional simulator is employed to account for various stress sources, such as thermal mismatch, grain growth and intrinsic stress. Factors such as process sequence, material properties and geometries are assessed to predict their impact on TSV reliability. Areas vulnerable to failure are identified and the failure mechanisms are analyzed in detail. Numerical analyses of electrical coupling between adjacent TSVs are also carried to examine the effects of TSV layout, material properties and geometries on TSV isolation performance. This study provides an important understanding of the factors that affect the TSV reliability and isolation performance, and guidelines for 3D integration improvements.
12:45 PM - F9.9
Investigation of Processing and Cure Parameters on the Electrical and Reliability Properties of Dispensable 3D Electrical Interconnects.
Suzette Pangrle 1 , K. Holcomb 2 , G. Villavicencio 1 , J. Leal 1 , S. McGrath 1 , S. McElrea 1 , M. Matthews 2 , J. Cabradilla 1 , B. Hankes 1 , J. Leff 1 , D. Melcher 1 , K. Barrie 1 , J. Bray 1 , R. Co 1 , M. Robinson 1 , S. Kaul 1
1 , Vertical Circuits Inc, Scotts Valley, California, United States, 2 , Ormet Circuits Inc, San Diego, California, United States
Show AbstractWith a need for smaller footprints, higher storage capacity, and multi-functional 3D structures, new innovative techniques for 3D interconnects are needed when traditional wire-bonding techniques become inadequate and where TSV is not a cost-effective solution. This paper discusses the metallurgical properties of highly reliable sidewall vertical interconnects. Material selection will vary according to pitch and electrical requirements. Material selection criteria will be reviewed. To meet these criteria, an investigation of the Temperature, Time and curing environment was studied to optimize the resistivity and reliability of these vertical interconnects. Electrical resistivity, Microscopy and EDX data will be presented to confirm the mechanism leading to the improvement. Thermal cycle results and wearout mechanism verified the results of the optimization.
F10: Emerging Interconnect Technologies
Session Chairs
Thursday PM, April 08, 2010
Room 2010 (Moscone West)
2:30 PM - **F10.1
Deterministic Assembly of Functionalized Nanowire Devices for Ultracompact Multiplexed Biosensor Chips.
Theresa Mayer 1 3 , Thomas Morrow 3 , Jaekyun Kim 1 , Wenchong Hu 1 , Christine Keating 3
1 Electrical Engineering, Penn State University, University Park, Pennsylvania, United States, 3 Materials Science and Engineering, Penn State University, University Park, Pennsylvania, United States, 3 Chemistry, Penn State University, University Park, Pennsylvania, United States
Show AbstractIntegrating functionalized nanowire sensors directly with Si integrated circuits (ICs) has the potential to combine highly selective and sensitive biorecognition with electronic signal processing in a single ultra compact, low power device. Such nanobiosensor chips may provide a solution for real time, point of care diagnostic systems by enabling simultaneous electrical detection of many different target molecules in a cost effective, user friendly system. However, conventional IC manufacturing methods place considerable limits on the range of materials and molecules that can be incorporated directly onto Si chips, making it difficult to realize this goal.This talk will provide an overview of a new deterministic assembly approach that uses electric field forces to direct different populations of bioprobe-coated nanowires to specific regions of the chip and to provide accurate registration between each individual nanowire and a specific transistor on the chip. This is achieved by synchronizing sequential injections of nanowires carrying different bioprobe molecules with a programmed spatially-confined electric field profile that directs nanowire assembly. Subsequent back-end lithographic and metal deposition processes are then used to electrically and mechanically connect all of the nanowire devices to the silicon chip at the same time. Using this technique, we have demonstrated individual nanowire device integration yields exceeding 90% with a less than 1% mismatch across three populations of DNA-coated nanowires for arrays with densities of 106 cm-2. The nanowire-bound DNA retained its ability to selectively bind complementary target strands following assembly and device fabrication showing that this process is compatible with these back-end manufacturing steps. The electrical properties of nanowire devices that have been fabricated using this hybrid integration strategy, including silicon nanowire field effect transistors, will also be discussed.
3:00 PM - F10.2
Selective Growth of Ge Quantum Wells on Si: Towards a Compact Monolithic Optical Modulator on SOI Waveguide Platform for Advanced Optical Interconnect Systems.
Shen Ren 1 , Yiwen Rong 1 , Theodore Kamins 1 , James Harris 1 , David Miller 1
1 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractOptical interconnect has been considered a promising candidate for future interconnect technology [1]. An optical modulator is a key building block for optical interconnect systems. Previously Ge quantum wells demonstrated strong quantum-confined Stark effect (QCSE) electroabsorption [2], making it an attractive material for optical modulation. In this work, the selective growth of Ge quantum well structure is investigated for the first time. Moreover, a monolithic QCSE modulator integrated with silicon-on-insulator (SOI) waveguide is proposed and analyzed.Selective growth of bulk Ge on Si has been investigated for optical detector applications [3]. In our work, we extend the selective growth to a more complex structure for optical modulator applications. 10 pairs of 15nm compressively-strained Ge quantum wells with 20nm Si0.15Ge0.85 barriers are embedded in the intrinsic region of a vertical p-i-n Si0.1Ge0.9 diode structure. The entire p-i-n structure is grown at 400oC on a pre-patterned (001) silicon substrate by reduced pressure chemical vapor deposition (RPCVD). The pre-patterned substrates have a 1.2µm thermal oxide, acting as growth mask, with growth seeding windows of different widths. Boron and Arsenic are incorporated in the p and n regions, respectively, through in-situ doping. Strong faceting is observed within 1µm next to the growth window boundary. Planar and uniform quantum well structures are grown away from the faceting region. Under our growth conditions, the grown thickness is independent of growth window size. Furthermore, we propose a novel approach to integrate selectively-grown Ge quantum wells into the SOI waveguide platform. SOI waveguides, acting as input and output passive waveguides, butt-couple to the selectively-grown Ge quantum well region. The active region is designed to be 50 µm long, within which the faceting region plays a negligible role (less than 5%). To avoid lateral growth and electrical shorting problems due to the crystalline facet of the SOI waveguide, an insulating layer, such as SiO2, should be implemented on the waveguide facet prior to the growth. According to finite-difference time-domain (FDTD) simulation, we find that, for insulating layers thinner than 10nm, more than 90% of the light can be coupled from the passive waveguide to the quantum well waveguide modulator. Experimentally, we designed and demonstrated a process to incorporate this interfacial layer for SOI waveguides. In summary, we have investigated the selective growth of Ge quantum well structures on Si and proposed an approach to integrate these selectively grown Ge quantum wells with the SOI waveguide platform. These results promise an efficient, compact, low power optical waveguide modulator for advanced optical interconnect applications. [1] D. A. B. Miller, Proc. IEEE 97, 1166 - 1185 (2009).[2] Y. H. Kuo et al., Nature 437, 1334-1336(2005). [3] L. Vivien, et al., Opt. Express 17, 6252-6257(2009).
3:15 PM - F10.3
Reliability Investigation of Carbon Nanotube-Electrode Interfaces for Interconnect and Via Applications.
Mark Strus 1 , Ann Chiaramanti-Debay 1 , Robert Keller 1
1 Materials Relability, National Institute of Standards and Technology, Boulder, CO, Colorado, United States
Show AbstractSingle and bundled carbon nanotubes (CNTs) have emerged as a potential alternative solution to copper for interconnect and via architectures as integrated circuits shrink to feature sizes below 45 nm. Carbon nanotubes have been shown to exhibit near ballistic flow of electrons, which promises large current densities and high conductivity superior to scaled-down copper wires.Furthermore, carbon nanotubes possess extraordinary mechanical strength, high resistance to electromigration, and enhanced thermoconductivity which may offer enhanced electrical performance and longer lifetime over current copper technology. Despite these advantages, the electrical reliability of carbon nanotubes, particularly the reliability of CNT-metal electrode interfaces has gone largely unstudied. In the current work, individual multiwalled carbon nanotubes welded to a Ni-coated probe and manipulated in a scanning electron microscope are brought into contact with various metallic surfaces to demonstrate which electrode types are ideal for long-term reliable performance. The CNTs interconnects are subject to both direct and alternating currents and exhibit very different failure modes, which depend on the electrical excitation, electrode material, and contact area. These failure modes, which are further classified in a transmission electron microscope, are used to provide a roadmap for future CNT interconnect design and fabrication.
3:30 PM - F10.4
Multilayer Graphene System: Key Reliability Limits for On-chip Interconnect Applications.
Tianhua Yu 1 , Eun-Kyu Lee 1 , Benjamin Briggs 1 , Bhaskar Nagabhirava 1 , Bin Yu 1
1 College of nanoscale science and engineering, University at Albany, State University of New York, Albany, New York, United States
Show AbstractScaling, power, and reliability issues in traditional metal (copper)-based interconnect have driven research towards alternative materials for next-generation interconnects technology for integrated systems. Recently, graphene has emerged as a highly competitive candidate for future on-chip interconnects due to its superior electrical transport characteristics and thermal conductivity. Particularly, bilayer graphene (BLG) can offer controllable band-gap tenability, and hence great potential in implementing new electronic devices. In this study, we aim at addressing two key reliability limiting factors with focus on (1) BLG-to-Cu contact reliability and (2) BLG current-carrying capacity/breakdown characteristics. It was observed that DC current-induced annealing will greatly reduce the BLG/Cu contact resistance, and contact damage plays a dominant role in electrical breakdown with dependency on contact area. It was also found that BLG exhibits an impressive breakdown current density, on the order of 10^8 A/cm2. The observed linear dependence of breakdown current on the width/length ratio (and hence electrical conductance) suggests Joule-heating as the primary breakdown mechanisms. Correlation of breakdown with local defectivity was also obtained. Similar measurements were observed in trilayer graphene (TLG) with slightly improved breakdown characteristics.
3:45 PM - F10.5
Nanometer Metrology of Periodic Structures With Ultrafast Optoacoustics.
Thomas Grimsley 1 , G. Andy Antonelli 1 , Humphrey Maris 1 , Arto Nurmikko 1 2 , Fan Yang 1
1 Physics, Brown University, Providence , Rhode Island, United States, 2 Division of Engineering, Brown University, Providence, Rhode Island, United States
Show AbstractIn the transition to 32nm node processes and beyond, the semiconductor manufacturing industry fabricates structures that are difficult to characterize non-destructively with existing techniques. We present an optoacoustic method to non-destructively measure the average dimensions of a periodic array of simple structures with aspect ratios greater than 10:1, which are inaccessible to AFM techniques. The technique that we describe could be used as the basis of an inline metrology tool for wafer inspection. The samples examined were test structures with high precision lithographically defined lines of silicon dioxide deposited on a silicon substrate. The thickness of the silicon dioxide was around 400 nm, and the gaps between the lines ranged from 100 nm down to smaller than 40 nm. A drop of water was placed on the sample, and an optoacoustic transducer was placed on top; measurements were taken with water thicknesses in the range of 500 nm to 2 microns between the optoacoustic transducer and the sample. The water filled the spaces between the lines due to the hydrophilic nature of the sample surface. Using the picosecond ultrasonics technique, acoustic pulses are generated in a special optoacoustic transducer, transmitted through a coupling fluid (water), scattered off of the sample being examined and then return to the transducer. The technique of picosecond ultrasonics uses pulses from a mode-locked laser to generate and detect sound pulses with durations on the order of picoseconds. An ultrashort light pulse (~150 fs) from the pump beam is absorbed by optoacoustic transducer. The energy deposited by the pump pulse generates an elastic stress; as this stress relaxes it launches an acoustic pulse into the coupling fluid. This pulse then propagates across the coupling fluid (water) and then reflects and scatters off of the sample. Returning sound that has been reflected and scattered from the sample modifies the optical reflectivity of the optoacoustic transducer. A probe pulse that has been delayed in its arrival time monitors changes in reflectivity caused by the returning sound. The optoacoustic transducer was a Fabry-Perot optical cavity structure, which was used to increase the change in optical reflectivity caused by returning sound pulses. The cavity consisted of films of aluminum, silicon dioxide, and aluminum with thicknesses of 7nm, 246nm, and 100 nm respectively. The thickness of the silicon dioxide layer was chosen such that the structure is just off resonance at the center wavelength of the laser. Returning sound changes the optical thickness of the silicon dioxide layer, which in turn causes a change in optical reflectivity that is detected by the probe beam. By fitting the experimental data to numerical simulation results, the height of the silicon dioxide lines can be determined with nanometer accuracy and additional information about the pitch and widths of the lines can be estimated.