Symposium Organizers
Christopher L. Borst SUNY-Albany College of Nanoscale Science and Engineering
Johann W. Bartha Technische Universitaet Dresden
Darren DeNardis Intel Corporation
Satyavolu S. Papa Rao IBM T.J. Watson Research Center
E1: CMP for Advanced Technology Nodes
Session Chairs
Tuesday PM, April 06, 2010
Room 2000 (Moscone West)
9:45 AM - **E1.1
CMP: An Enabler for Transistor Technology.
Gary Ding 1
1 Portland Technology Development, Intel, Hillsboro, Oregon, United States
Show AbstractWith continued relentless march of Moore’s law demanding patterning precision down to single nanometers, exploding use of a wide variety of materials with over 50% of elements on earth reportedly used in semiconductor processing, chemical mechanical polish (CMP) in front end plays a critical and enabling role in defining topography to enable patterning and construction of transistors due to its ever increasing presence in the process flow.Intel’s 45 nm HiK-metal gate technologies was a perfect example highlighting the criticality of CMP in semiconductor processing. There were two new CMP steps involved: poly opening polish as well as metal gate polish. These two applications were instrumental in enabling Intel’s HiK-metal gate technology. The challenges were daunting. Not only did these applications require simultaneous removal of heterogeneous materials, the flatness across wafer and within die, as well as accuracy for thickness targeting is on the order of nanometers or even sub-nanometers. In addition, even shallow scratches sub-nanometer in depth and tiny particles of that magnitude can easily become die killers. All these defects must be eliminated to have a viable manufacturing process. Despite these challenges, Intel recorded highest yield ever with 45 nm technology node, and CMP defect reduction played a significant role in enabling this yield.Front end CMP applications such as these, require rapid innovation and high intensity development since materials selection to product to market time could be exceedingly short. That type of innovation cannot happen at IC makers only. It is imperative that all participants, from academia, to materials and equipment makers (both polish and metrology) as well as IC makers, actively and aggressively pursue innovative ideas, and deliver cost effective solutions. There are many exciting opportunities for nimble players in this wide open field.
10:15 AM - E1.2
Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications.
Jamal Qureshi 1 2 , Stephen Olson 1 2 , Raymond Caramto 1 2 , Jerry Mase 1 2 , Toshihiro Ito 3 , Eiichi Yamamoto 3
1 College of Nanoscale Science & Engineering, SUNY, Albany, New York, United States, 2 3D Interconnect, SEMATECH, Albany, New York, United States, 3 Process R&D, OKAMOTO Machine Tool Works,LTD., Annaka, Gunma, Japan
Show Abstract3D interconnect wafer-to-wafer or die-to-wafer integration flows require a wafer thinning operation to expose Cu-filled through-silicon vias (TSVs) from the backside of the wafer. This integration sequence utilizes edge trim, backgrind, backpolish, and CMP. This paper gives an overview of wafer grinding process techniques. We have demonstrated capabilities to edge trim and backgrind 300mm TSV and non-TSV wafers down to 30 microns while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by AFM to observe surface roughness and by TEM to quantify crystalline damage below the surface of the thinned wafer. Further characterization was accomplished by measuring wafer thickness, TTV, bow, and warp. Exposed TSVs were characterized by laser microscope to measure the protruded Cu height. These critical elements of a manufacturing-worthy 300mm wafer thinning process for 3D will be discussed.
10:30 AM - **E1.3
An Approach to the Integration of CMP Processes for Interconnects at the 15nm Node.
Donald Canaperi 1
1 , IBM, Albany, New York, United States
Show Abstract11:30 AM - E1.4
Planarization Specification for 22nm and Beyond BEOL CMP.
Jihong Choi 1 , Bernhard Liegl 2 , Changan Wang 1 , Itty Matthew 1 , Eden Zielinski 1 , Wei-tsu Tseng 2 , Yongsik Moon 1 , Mark Kelling 1 , Laertis Economikos 2 , Seung-Hyun Rhee 1 , Raghavasimhan Sreenivasan 2 , Edward Engbrecht 2
1 , GlobalFoundries, Hopewell Junction, New York, United States, 2 , IBM Microelectronics, Hopewell Junction, New York, United States
Show AbstractIn back end of line (BEOL) interconnect metal layers, small pitch layers (thin wire) that have tight litho depth of focus (DOF) requirement are formed first and larger pitch layers (fat wire) that have more room for DOF are formed later on top of thin wire layers. Hence, topography specification for top metal layers can be less aggressive even though those layers have larger topography than lower layers. However, in many logic applications using sub-32nm technology nodes, more than five thin wire layers are required, and predicting process feasibility for BEOL metal layers stack options in advance is very critical in the process development stage. Since CMP is one of the last process steps before lithography that is directly related to the planarization of wafer surface, CMP topography specification is a key parameter to characterize the feasibility of a given BEOL stack option. CMP-induced topography is systematic largely in three different lateral scales; wafer scale, die scale, and feature scale. Today, optical or mechanical detection of long range wafer surface height variation and focus adjustment is possible in most advanced lithography systems. However, feature scale topography cannot be compensated in the litho step since it is within an individual exposure field. Hence, topography specification in feature scale is most critical for CMP process development from a lithography perspective. In addition, local topography is important since it can cause so called ‘puddle’ defects in subsequent layers. If local erosion is too great, the CMP process in the next layer cannot remove metals within the recessed area causing residual metal and short problems.In this study, topography specification for 22nm and beyond CMP process is discussed and recent experimental data is presented. We evaluated local topography impact on CD development in the subsequent layer using specially designed 22nm test patterns. A wide range of localized erosions were generated in CMP within a single exposure field to avoid any focus correction effect by the scanner or any other scanner induced focus change between different levels of local erosion. Local erosions were measured by Atomic Force Microscopy (AFM) after each process step from CMP to lithography to know the local planarization effect from other film coatings between CMP and lithography. Post litho CD inspection was done in the subsequent layer over the local erosion areas. Then, metallization continued and post CMP inspection was done at the same locations to check puddle generation. With experimental results, BEOL pattern design rule for maximizing process window is also discussed.
11:45 AM - E1.5
Molecular Diffusion Under Nanometer Scale Confinement During CMP of Nanoporous Films.
Taek-Soo Kim 1 , Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States
Show AbstractCMP slurries and post-CMP cleaning solutions contain surfactants and organic molecules that can significantly enhance the diffusion of aqueous solutions in nanoporous ultra-low-k (ULK) films. We present a fundamental study to elucidate the effects of molecular diffusion in nanoporous films with selected pore size and porosity. We show that the conventional free volume dependent mobility relationship explained by the free volume theory of diffusion breaks down for diffusion of linear alkane molecules in organosilicate films with connected nanoporosity. Alkane mobility under such nanoscale confinement was observed to decrease with chain length and was lower than that reported in the bulk. While the activation energy for diffusion was similar to that in the bulk, it was found to decrease with chain length exactly opposite to the trend observed in the bulk. The effects of molecular polarity and pore size on diffusion were also demonstrated. Molecular mobility was found to be suppressed with increasing molecular polarity and decreasing pore size. Finally, we consider the molecular mobility of nonionic surfactants including polyoxyethylene alkyl ethers and dimeric (branched) gemini surfactants which are ubiquitous additions to slurries and cleaning solutions. We demonstrate that the surfactant molecules themselves can diffuse into ULK films with diffusion coefficients sensitive to molecular weight, hydrophilic-lipophilic balance and molecular structure. Analysis of the measured diffusion coefficients reveals that short-chain surfactants exhibit signatures of reptation based diffusion under nanoscale confinement. The study has significant implications for CMP of nanoporous films.
12:00 PM - E1.6
Cu CMP Edge Uniformity Improvement Studies for 32 nm Technology Node and Beyond.
John Zhang 1 , Laertis Economikos 2 , Wei-Tsu Tseng 2 , Jihong Choi 3 , Qiang Fang 3 , Teck Jung Tang 3 , Joe Salfelder 4 , Connie Truong 2 , Paul Ferreira 1
1 , STMicroelectronics, Hopewell Junction, New York, United States, 2 , IBM Semiconductor Research and Development Center (SRDC), Hopewell Junction, New York, United States, 3 , Global Foundries Inc, Hopewell Junction, New York, United States, 4 , Applied Materials, Hopewell Junction, New York, United States
Show AbstractStudies of the edge uniformity step by step, from hard mask deposition, reactive ion etch, electroplating to post Cu CMP had been done using extensive scanning electron microscopy (SEM) measurements and showed that the non-uniformity comes from the Cu CMP step. Improvement of Cu CMP edge uniformity had been achieved through engineering of platen 1 using real time profile control as well as CMP head zone pressure adjustment and platen 3 slurry optimizations. This work was performed at the IBM Microelectronics Div. Semiconductor Research and Development Center Hopewell Junction, NY 12533.
12:15 PM - E1.7
Copper CMP for TSV Applications.
Max Gage 1 , Kun Xu 1 , Feng Liu 1 , Yuchun Wang 1 , Sherry Xia 1 , Wen-Chiang Tu 1
1 CMP Division, Applied Materials, Santa Clara, California, United States
Show AbstractThrough-silicon via (TSV) 3-D packaging and integration presents many new opportunities and challenges for metals CMP application. For front-side TSV polishing, challenges include the removal of large amounts of copper overburden following plating, dishing control during copper clearing steps, and large amounts of barrier metal and dielectric to be removed while still maintaining control over topography and defectivity. Additionally, the choice of barrier material can have significant impact on polishing and mechanical reliability regarding adhesion between the barrier metal and underlying dielectric layers. This presentation will address many of these challenges with emphasis on innovative technologies for superior process and endpoint controls, including real-time profile control for thick copper films up to 6um or more in thickness and automatic endpoint controls for barrier removal and dielectric stopping. The presentation will also discuss some salient challenges for back-side TSV polishing, including the handling and polishing of bonded wafer pairs and strategies for the elimination of handling and polishing damage to the potentially fragile thinned device wafer. Additionally, the development of slurries with highly tunable copper to dielectric selectivities will be critical for enabling a wide range of final topographies, depending on requirement for subsequent bonding steps.
12:30 PM - E1.8
High Removal Rate CMP Process on TSV Thick Cu Overburden.
Raymond Caramto 1 2 , Jamal Qureshi 1 2 , Jerry Mase 1 2
1 3D Interconnect, College of Nanoscale Science and Engineering, RF of SUNY, Albany, New York, United States, 2 3D Interconnect, SEMATECH, Albany, New York, United States
Show AbstractIn 3D packaging, Through Silicon Vias (TSVs) with high aspect ratios and depths measuring tens of microns are filled by advanced Cu electroplating processes. TSV plating on today’s 300mm platforms is intended to produce bottom-up via fill, no seam voids, and very minimal controlled overburden. To achieve this ideal performance, the preceding Cu-seed coverage must be continuous at a constant resistance, and the plating chemistries optimized. However, other factors such as hardware configurations and simple depletion of the plating formulations during the extended TSV plating process can lead to high Cu thickness that requires a high removal rate (RR) chemical-mechanical polish (CMP) process to remove the thick overburden Cu layer. Presented here are results of the CMP of a thick Cu overburden (~6um) resulting from the fill of 5 x 25um TSVs on 300mm wafers. The goal is to uniformly polish the thick Cu overburden and utilize the tool’s endpoint system at Cu clear before the next step of conventional barrier CMP. Slurries were screened for removal rate, uniformity, planarization ability, and defectivity. This study focuses on achieving a removal rate of ~ 2.5um/min through evaluation of several commercial slurries in a multi-step polish application. Cross-sections post-plating show the Cu overburden, barrier and liner layer. Cross-sections post-CMP quantifies Cu recess, dielectric loss, and presence/absence of seam defects. The process selected is demonstrated to achieve good planarization results with low polish defects, at a rate and selectivity suitable for emerging 3D TSV Cu CMP applications.
12:45 PM - E1.9
Reducing Time Dependent Line to Line Leakage Following Post CMP Clean.
Donald Canaperi 1 , Satyavolu Papa Rao 2 , Trace Hurd 3 , Steven Medd 3 , T. Levin 1
1 , IBM at Albany Nanotech, Albany, New York, United States, 2 , IBM Research, Yorktown Heights, New York, United States, 3 , ATMI Inc., Danbury, Connecticut, United States
Show AbstractPost-CMP corrosion of copper interconnects has been observed in earlier technology nodes. But at the 32/22nm nodes and beyond, it has become a critical problem that can impact yield and reliability due to decreasing line spacing, dielectrics with lower k-values, and other factors that increase the propensity for Cu corrosion. An opportune time to apply a passivating film on the exposed copper surface is during post-CMP cleaning – since it is done immediately following CMP, in the same tool. A good passivating film is one that prevents corrosion until the deposition of a capping layer, and does not degrade physical metrics (such as defectivity) and electrical characteristics of the Cu interconnect. In this study, a systematic approach was taken to identify passivating agents that are effective in preventing corrosion in 22nm interconnect structures. In general, the passivating agents fall into one of two categories: 1) Cu ion complexants with film forming properties and 2) surface active compounds that preferentially attach to Cu oxide surfaces. Prior to patterned wafer testing these passivating agents were prescreened and optimized using both surface and solution analytical techniques, including light scattering, surface FTIR, and turbidity measurements. The resulting films on test wafers were evaluated in multiple ways, including defectivity, morphology by SEM, and electrical tests such as leakage of minimum pitch arrays as well as the resistance of narrow lines. Feasibility of using the novel passivating agents at the 22nm node for Cu interconnects was demonstrated. A simple model was developed to explain the effects of the various passivating agents on the electrical characteristics of the interconnect.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities
E2: CMP Consumables I
Session Chairs
Tuesday PM, April 06, 2010
Room 2000 (Moscone West)
2:30 PM - **E2.1
Retaining Ring Design Impact on CMP Process Stability and Optimization.
Christopher Wargo 1 , Raghava Kakireddy 1 , Andrew Galpin 1 , Joseph Smith 1 , Rakesh Singh 1 , Xiaomin Wei 2 , Ara Philipossian 2 3
1 , Entegris, Inc., Billerica, Massachusetts, United States, 2 , University of Arizona, Tucson, Arizona, United States, 3 , AracA, Inc., Tucson, Arizona, United States
Show AbstractThe focus of this work is wafer retaining rings and their impact on CMP process stability, yield, and overall Cost Of Ownership (COO). The initial phase of the study looks at various retaining ring materials and processing methods. Tribological investigations prior to wafer processing are critical to understand the retaining ring/polishing pad environment. Interactions at the ring/pad interface have a major effect on CMP of the wafer. Shear and normal forces at this interface, as well as temperature and lubrication regimes, were monitored to establish a working model. All process conditions equal, the material properties of retaining rings govern the Coefficient of Friction (CoF) in the ring/pad contact area; a lower CoF was shown to be an indicator of extended ring lifetime, decreasing WTWNU and removal rate (RR) variation. A second phase of the study modulated retaining ring geometry to determine its influence on slurry movement and pad texture, and ultimately, processed wafer properties. Dual Emission Ultra-Violet Enhanced Effluorescence (DEUVEF) techniques were used to measure slurry thickness on the pad and under the wafer. After establishing a correlation for slurry dispensed to the pad, slurry thickness, and wafer properties such as WIWNU, RR, and defects, alternate ring geometries were developed and tested. A preliminary ring geometry design model was established that maintains slurry thickness under the wafer at reduced slurry flow rates and reduces any changes to WIWNU and defects as compared to a standard retaining ring geometry. The impact on wafer RR and RR profiles were minimized as well. Ring geometry was also correlated to pad texture and pad wear to more fully understand the total process effect. CMP process optimization can be clearly attained with a better understanding of retaining ring design, and polishing head and slurry parameters.
3:00 PM - E2.2
Real-time Control System for Improved CMP Pad Profiles.
Gregory Menk 1 , Siva Dhandapani 1 , Chad Garretson 1 , Shou-Sung Chang 1 , Chris Cocca 1 , Jason Fung 1 , Jun Qian 1 , Stan Tsai 1
1 , Applied Materials, Sunnyvale, California, United States
Show AbstractChemical mechanical planarization (CMP) pads require periodic conditioning to maintain surface finishes yielding optimal performance. However, conditioning not only regenerates the pad surface but also wears away features used for distribution of fresh slurry and for waste product removal. Non-optimized conditioning may result in non-uniform pad profiles, limiting the productive lifetimes of pads. A new approach to conditioning uses closed-loop control (CLC) of conditioning sweep to enable uniform groove depth removal across the pad, throughout pad life. A sensor integrated into the conditioning arm enables the pad stack thickness to be monitored in-situ and in real time. Feedback from the thickness sensor is used to modify pad conditioner dwell times for each zone in the sweep schedule, correcting for drifts in the pad profile that may arise as the pad and disk age. Pad profile CLC enables uniform reduction in groove depth with continued conditioning, providing longer consumables lifetimes and reduced operating costs.
3:15 PM - E2.3
Reducing CMP’s Cost of Consumables by Improving Its Efficiency Through Pad Surface Management.
Darryl Peters 1 , Stephen Benner 1 , Gilberto Perez 1
1 Process Technology, Confluense, Allentown, Pennsylvania, United States
Show AbstractThe efficiency of CMP processes for rotary tools has been studied by numerous tool and material suppliers, as well as by academic professionals. It has been generally agreed that the process is not very efficient. A significant fraction of delivered slurry does not participate in the polish process and is sent directly to waste. Pads are over dressed leading to a shorter operational life, and tools recycle polish byproducts and pad debris under the wafer leading to poor surface finish (i.e., scratches, microscratches, chatter marks, etc.) and defectivity (i.e., particles). The typical rotary polishing tool uses a slurry dispense system to deliver fresh slurry to a pad surface that is saturated with spent slurry and polish byproducts. The pad area has grooves intended to distribute slurry, representing a significant non working volume. A conditioning mechanism is used to mix fresh slurry with materials already present on the pad by using a diamond abrasive disk, resulting in persistent dressing of the pad and thus decreasing its life time. The net effect is that a typical process of record (POR) will flood the pad with slurry in an attempt to compensate for the impact of dilution by spent slurry and polishing debris. The major contributors to the cost of ownership (CoO) for CMP are slurry and pads. New technology will be introduced which consists of a retrofitable conditioning arm (the Pad Surface Manager, PSM) that allows removal of spent slurry and polish debris from the pad in-situ. Instead of ‘tilling’ the pad to mix fresh slurry with byproducts, the evacuated pad pores receive fresh slurry on every revolution, resulting in more stable material removal rates (MRR), reduced slurry consumption, lower wafer defects, and longer pad life. Data will be presented showing equivalent or higher MRR with reduced slurry flow rates for a variety of pad configurations, an increase in pad life, and a reduction in wafer defects when using PSM.
3:30 PM - **E2.4
Design, Characteristics and Performance of Diamond Pad Conditioners.
Douglas Pysher 1 , Brian Goers 1 , John Zabasajja 1
1 Electronics Markets Materials Division, 3M, St. Paul, Minnesota, United States
Show AbstractA wide range of pad conditioner (disk) designs have been characterized and key performance metrics have been collected. Relationships between design characteristics including diamond size and shape, spatial density, and tip height distribution and CMP pad wear rates and pad surface textures have been established for a variety of CMP pads.Estimation of the depth-of-penetration of working diamonds, from used disk analyses, allows meaningful topographic assessments of alternative conditioner designs and predictions of relative performance. Examples of improved conditioner designs illustrating this design methodology are given.Conditioner aggressiveness and its decay in various slurries has been measured to assess disk lifetime in CMP processes environments. Key factors affecting disk lifetime are discussed and an improved-lifetime conditioner for use in aggressive slurries will be reviewed.
4:30 PM - E2.5
Method for Ultra-rapid Determination of the Lubrication Mechanism of CMP Processes.
Yasa Sampurno 1 2 , Sian Theng 1 2 , Fransisca Sudargho 1 2 , Yun Zhuang 1 2 , Ara Philipossian 1 2
1 Chemical Engineering, University of Arizona, Tucson, Arizona, United States, 2 , Araca, Inc., Tucson, Arizona, United States
Show AbstractIn CMP, as a first approximation, the Stribeck curve helps provide evidence of the extent of contact among wafer, pad and abrasive particles where three major lubrication modes can be distinguished. The first mode is ‘boundary lubrication’ where all solid bodies are assumed to be in intimate contact with one another. In this case (which is preferable in CMP) the coefficient of friction (COF) does not depend on the Sommerfeld number. The second mode is ‘partial lubrication’ where the wafer and the pad are partially contacting each other. Finally, the ‘hydrodynamic lubrication’ mode occurs when the fluid film layer separates the pad and the wafer, and COF once again becomes independent of the Sommerfeld number, albeit at a much lower value. In practice, the Stribeck curve can help in screening certain consumable sets (i.e. pad, slurry, wafer, retaining ring and conditioner disc) by determining if and how they contact one another during CMP and can help in determining the optimal polishing parameters (i.e. wafer, retaining ring and diamond disc pressure, as well as slurry flow rate and tool kinetamics). Traditionally, constructing the Stribeck curve for a given consumables set involves calculating the COF (by knowing the fixed down force and by measuring the shear force in real-time). Since a wafer needs to be polished to obtain the COF at a given polishing pressure and sliding velocity, constructing the Stribeck curve requires polishing wafers at various pressures and sliding velocities (as many as 20 polishing runs are required in most cases) which is quite costly and time consuming. This paper presents a new method for obtaining the Stribeck curve corresponding to a set of consumables in CMP by only performing one wafer polishing experiment. This new method, which is also more accurate and cost effective, is accomplished by use of polishers capable of simultaneously measuring shear force and down force, and rendering a value for COF while simultaneously enabling a multitude of changes in pressure and velocity in real-time. In a given run, pressure and sliding velocity are varied separately or together for a desired length of time so that multiple measurements can be taken within one run. This paper also discusses several Stribeck curves resulting from various polishing substrates (i.e. blanket copper and silicon dioxide wafers as well as various retaining ring materials and designs) using different types of polishing pads, slurries and conditioning discs.
4:45 PM - E2.6
Tribological and Kinetic Characterization of 300-mm Copper Chemical Mechanical Planarization Process.
Yubo Jiao 1 , Anand Meled 1 , Xiaomin Wei 1 , Zhenxing Han 1 , Jiang Cheng 1 , Yasa Sampurno 1 2 , Yun Zhuang 1 2 , Mansour Moinpour 3 , Don Hooper 4 , Ara Philipossian 1 2
1 Chemical and Environmental Engineering, University of Arizona, Tucson, Arizona, United States, 2 , Araca Inc., Tucson, Arizona, United States, 3 , Intel Corporation, Santa Clara, California, United States, 4 , Intel Corporation, Albuquerque, New Mexico, United States
Show AbstractThe tribological and kinetic attributes of 300-mm copper chemical mechanical planarization (CMP) process were characterized in this study. All experiments were performed on an Araca APD-800 polisher and tribometer equipped with the unique ability to acquire real-time shear force and down force data critical for determining the coefficient of friction (COF) and lubrication mechanism. Two different pads, (i.e. Dow Electronic Materials IC1000 K-grooved pad and Cabot Microelectronics Corporation D100 concentrically grooved pad), were used to polish blanket 300-mm copper wafers. Prior to data acquisition, each pad was conditioned for 30 minutes using ultra-pure water and a new Shinhan diamond disc rotating at 95 RPM and sweeping at 0.33 Hz. The load applied to the diamond disc was 2.7 kgf. The same load, rotational velocity and oscillation frequency were used for in-situ pad conditioning. The diamond disc, pad and wafer were rotated counter-clockwise during polishing. For each pad, wafers were polished with Cabot Microelectronics Corporation iCue 600Y75 slurry under three polishing pressures (6.9, 11.7 and 17.2 kPa) and three pad-wafer sliding velocities (0.6, 1.0 and 1.5 m/s) for one minute. The slurry flow rate was maintained at 300 ml/min. The COF ranged from 0.37 to 0.62 for the D100 pad, indicating boundary lubrication was the dominant tribological mechanism. In comparison, the COF decreased sharply from 0.50 to 0.04 for the IC1000 pad, indicating there was a mechanism transition from boundary lubrication to partial lubrication. For both pads, the copper removal rate did not increase linearly with the polishing power (product of polishing pressure and wafer/pad sliding velocity), exhibiting highly non-Prestonian behavior. A two-step modified Langmuir-Hinshelwood model was used to simulate copper removal rate, wafer surface reaction temperature, as well as the chemical and mechanical rate constants. The simulated copper removal rate agreed very well with the experimental values and the model successfully captured the highly non-Prestonian removal rate behavior. The chemical rate constant (k1), mechanical rate constant (k2) and the ratio of two constants (k1/k2) were analyzed and compared using the Wilcoxon signed-rank test. There was no significant difference in k1 between the two pads. Due to a lower COF value, the IC1000 pad resulted in a lower mechanical rate constant and therefore a higher k1/k2 ratio, indicating that the IC1000 pad generally produced a more mechanically controlled removal mechanism.
5:00 PM - E2.7
Effect of Mechanical and Chemical Wear on Consistency of Conditioning in Diamonds.
Yohei Yamada 1 , Kazunori Kadomura 2 , Masanori Kawakubo 1 , Takahiro Sugaya 1 , Osamu Hirai 1 , Ken Tsugane 1
1 Micro Device Division, Hitachi, Ltd., Ome-shi, Tokyo, Japan, 2 Semiconductor Group, A.L.M.T.Corp., Osaka-shi, Osaka, Japan
Show AbstractAs electronic devices become smaller and integrated circuits become increasingly more complex, chemical-mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it achieves sufficient planarity in the interlevel dielectric layers for creating of ultra large-scale integration (ULSI) devices. The polishing pad characteristics significantly influence the planarization performance of CMP, and pad conditioning is also a crucial step in CMP. Pad surface conditioning using a diamond grid conditioner is performed both before and during CMP. The diamonds on the disc cut the pad surface, maintaining it against abrasive wear, plastic deformation, and debris accumulation. There is a clear relationship between the decrease in the polish removal rate and the reduction in asperity height on the pad due to the CMP polish removal rate sensitivity to the CMP pad structure. Pad conditioning is also necessary to open up the closed cells in the pad and to provide a consistent pad surface throughout the pad’s lifetime. Therefore, it is crucial to understand the degrading factors of a conditioning process and to optimize the design of the pad conditioner. In this study, we evaluated the effects of the edge degradation of diamonds in terms of their cutting ability from the viewpoint of mechanical, chemical and chemical-mechanical wear in CMP systems for high-volume manufacturing. This study focused on determining the correlation between the wear type of conditioning diamond disc and the pad cut rate. We found that micro-chipping on the cutting edges of a diamond caused by mechanical shock testing rapidly degraded the pad cut rate, while no adverse effects on the cutting ability were observed during the acidic slurry immersion test, and that decrease in cutting ability as the diamond sharp edges rounded off also caused a decline in the cut rate. Furthermore, a positive correlation was observed between the pad cut rate degradation and the tribological behavior of the ex situ conditioning procedure. The results showed that coefficient of friction (COF) during the pad conditioning increased as more truncation of asperity tip by wear and plastic deformation occurred. While the micro wear of diamonds in the pad conditioning dose occur, it is important to have a large number of diamond grids in contact with the pad to be used as a working grid in order to maintain the CMP performance.
5:15 PM - **E2.8
Selected Topics on Wear Phenomena in CMP.
Ara Philipossian 1 2 , Yun Zhuang 1 2 , Yasa Sampurno 1 2
1 , University of Arizona, Tucson, Arizona, United States, 2 , Araca Inc, Tucson, Arizona, United States
Show AbstractThis presentation will present several selected topics on wear phenomena in CMP.
E3: Poster Session: CMP as a Semiconductor Technology Enabler
Session Chairs
Tuesday PM, April 06, 2010
Exhibition Hall (Moscone West)
6:00 PM - E3.1
Comparison of H2O2 and KMnO4 as Oxidizer in Ge2Sb2Te5 Chemical Mechanical Polishing.
Hao Cui 1 2 , Jae-Hyung Lim 1 3 , Jin-Hyung Park 1 , Hyung Soon Park 4 , Ungyu Paik 5 , Jea-Gun Park 1 2
1 Advanced Semiconductor Materials and Devices Development Center, Hanyang University, Seoul Korea (the Republic of), 2 Department of Electronics & Communications Engineering, Hanyang University, Seoul Korea (the Republic of), 3 Department of Nanoscale Semiconductor Engineering, Hanyang University, Seoul Korea (the Republic of), 4 Advanced Process Research & Development Division, Hynix Semiconductor Inc., Icheon Korea (the Republic of), 5 Division of Advanced Materials Science Engineering, Hanyang University, Seoul Korea (the Republic of)
Show AbstractX-ray photoelectron spectroscopy (XPS) and electrochemical techniques are used to investigate the mechanism of polishing polycrystalline Ge2Sb2Te5 (c-GST) with potassium permanganate (KMnO4) and hydrogen peroxide (H2O2) in an alkaline environment. The polishing rate and the surface characteristics of c-GST are totally different in KMnO4- and H2O2-based slurry. It is found that c-GST polished in slurry with 0.3 wt% KMnO4 has a high polishing rate and good surface characteristics. In addition, a static etch test is carried out to quantitatively estimate the effect of chemical reactions on the polishing rate. The etch rate of c-GST in H2O2based slurry correlates well with the polishing rate, while that in KMnO4-based slurry is significantly suppressed. The suppressed etch rate is attributed to the formation of surface passive oxide layers, which is demonstrated by XPS measurement. Also, electrochemical impedance spectroscopy is used to confirm formation of the surface passive layer observed by XPS. Thus, permanganate can be used as an effective oxidizer in the c-GST chemical mechanical polishing process.Acknowledgement* This work was financially supported by the Acceleration Research Program of the Korea Science and Engineering Foundation and the Brain Korea 21 Project in 2009. We thank Mr. Manabu Kanemoto of SUMCO Corp. and Hynix Semiconductor Inc. for helping us with our experiments.
6:00 PM - E3.2
Effect of Slurry pH and H2O2 on Crystalline Ge2Sb2Te5 CMP Performance for PRAM Device.
Jong-Young Cho 1 2 , Jin-Hyung Park 2 , Hyung-Soon Park 3 , Ungyu Paik 4 , Jea-Gun Park 1 2
1 Department of Nanoscale Semiconductor Engineering, Hanyang university, Seoul Korea (the Republic of), 2 Advanced Semiconductor Materials and Devices Development Center, Hanyang university, Seoul Korea (the Republic of), 3 Advanced process research & development division, Hynix, Icheon-si Korea (the Republic of), 4 Division of Advanced Materials Science Engineering, Hanyang University, Seoul Korea (the Republic of)
Show AbstractChemical mechanical polishing (CMP) is an essential process for manufacturing of the phase change random access memory (PRAM) device below 50 nm design rule to achieve flat surface and separate phase change material such as Ge2Sb2Te5 (GST) surrounded by dielectric SiO2 in the confine GST cell structure. To avoid dishing of GST, erosion of SiO2, GST CMP requires a high polishing rate selectivity of GST-to-SiO2 film. Thus, we investigated the effect of pH and H2O2 on polishing rate of GST film using colloidal silica based slurry. Polishing test of GST film in slurry at acidic (~pH 2), near neutral (~pH 7), alkaline (~pH 10) conditions with and without H2O2 was performed using commercial 8” GST and SiO2 blanket wafers. As a result, the polishing rates of GST film were less than 20 nm/min in the absence of H2O2 regardless of slurry pH. However, when each slurry contains H2O2, polishing rate of GST film increased three times higher over 60 nm/min, and increased with a sequence of acidic, alkaline and neutral slurry. To understand the polishing mechanism of GST and SiO2 film, we measured potentiodynamic curve, secondary abrasive size and zeta potential of the slurry. The tendency of corrosion current density was similar to that of polishing rate, indicating that GST film with acidic and alkaline slurry combined with H2O2 underwent higher chemical effect such as oxidation and dissolution process.Therefore, it is suggested that alkaline slurry with H2O2 is suitable for high polishing selectivity. Acknowledgement* This work was financially supported by the Acceleration Research Program of the Korea Science and Engineering Foundation and the Brain Korea 21 Project in 2009. We thank Sumco Corp. and Hynix Semiconductor Inc. for helping us with our experiments.
6:00 PM - E3.3
The Mechanism of Haze and Defectivity Reduction in a New Generation of High Performance Silicon Final Polishing Slurries.
Michael White 1 , Richard Romine 1 , Lamon Jones 1 , Jeffrey Gilliland 1
1 , Cabot Microelectronics, Aurora, Illinois, United States
Show AbstractSilicon substrates have been polished with high pH, silica based slurries for many years. However, the introduction of ever-smaller features for advanced IC devices is driving the demand for slurries with improved surface quality. In this study, we will discuss a novel approach for reducing the particle defects and haze on silicon wafers. Such slurries can polish silicon surfaces to haze values below 0.030 ppm while maintaining removal rates of over 900 Å/min. This can enable a reduction in polishing time vs. commercially prevalent slurries and lead to a lower slurry usage that can translate directly into a lower cost per wafer. The mechanism of defectivity reduction is thought to involve the adsorbtion of additive molecules to the Si wafer surface tailored to the appropriate interaction energy to create a steric barrier between the abrasive particles and the substrate. For haze reduction, the interaction energy needs to be balanced such that the removal rate remains high on the peaks of the initially rough substrate where the kinetic energy of the particle is higher with locally higher pressures and shear rates while being high enough to inhibit polishing in the valleys. Lower roughness translates into less reflected light and a lower haze. Residual particles scatter light and also increase haze. We believe that residual particles can be reduced by creating a steric barrier between the particle and wafer that is sufficient to minimize covalent bonding between the substrate and particle. In addition to a wealth of polishing evidence, including process and temperature studies, further mechanistic work includes adsorbtion studies on both the wafer and particle surface.
6:00 PM - E3.5
Digital CMP Technology for Ultra Large Wafers.
Abhudaya Mishra 1 , Rajiv Singh 1 , Deepika Singh 1 , Purushottam Kumar 1
1 , Sinmat Inc., Gainesville, Florida, United States
Show AbstractThe semiconductor device industry is continually driven to improve performance and lower manufacturing costs by innovations such as increase in wafer size (up to 450 mm). With the transition to larger wafers, several challenges arise related to CMP technologies. The current CMP technology is not inherently scalable as a large number of process variables can cause widespread fluctuations in the polishing uniformity and planarity. Use of standard equipment for larger wafers is expected to decrease yield substantially. We have proposed a new Digital CMP (DCMP) process/technology that is independent of most variables (such as flow rate, pressure, etc.) encountered in conventional CMP processes. This non-Prestonian behavior facilitates digital, quantized removal of material. The DCMP technology is far superior in achieving high surface uniformity and planarity, as opposed to the current Analog industrial processes. Using this technology, the within-wafer non-uniformity was reduced to less than 2%, with minimization of edge effects.
6:00 PM - E3.6
Ultra-rapid Reactive Chemical Mechanical Polishing Process for Production of Contamination-free, Damage-free GaN Surfaces.
Arul Chakkaravarthi Arjunan 1 , Rajiv Singh 2 1 , Deepika Singh 1
1 , Sinmat, Gainesville , Florida, United States, 2 Materials Science Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractGaN free-standing substrates are ideal for the fabrication of III-V high-power and high-frequency devices. However, three outstanding surface related challenges limit the formation of high quality GaN substrates. First, the CMP induced surface contamination layer comprising of silicon, oxygen, and carbon induces an additional surface charge layer in the epi-films. Secondly, the surface and sub-surface polishing damage creates defects during growth. Thirdly, the current polishing techniques are rather slow which decreases throughput and increases the probability of surface damage and also produces surface defects such as pits. Currently, the polishing methods typically use colloidal silica particles (30-100 nm). Such particles contaminate the surface with silicon which leads to surface charge effects in GaN high-power, high-frequency devices. Furthermore, the extremely slow (30-50 nm/hr) polishing rates increases the cost of manufacturing and exposes the surface to surface damage due to extended polishing times. To address these challenges, we have developed novel Ultra-Rapid Reactive Chemical Mechanical Polishing (RCMP) process for production of contamination-free, damage-free GaN surfaces. The RCMP process is a sub-set of the chemical mechanical polishing (CMP) process and is characterized by the use of new nanoparticles under appropriate chemistry, surfactant and pH conditions, to induce oxidation of gallium nitride surfaces. Such polishing has eliminated contamination, subsurface damage, and produced atomically terraced surfaces. Further, Schottky barrier diodes fabricated on such surfaces have shown better characteristics. The process will be detailed and surface characterization results (XPS, AFM) will be presented in the full length article.
6:00 PM - E3.7
Novel Method for Ultra-smooth Polishing of Diamond Thin Films.
Arul Chakkaravarthi Arjunan 1 , Rajiv Singh 2 1 , Deepika Singh 1
1 , Sinmat, Gainesville , Florida, United States, 2 Materials Science Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractThe ability to fabricate ultrasmooth diamond thin films is expected a number of commercial applications such as MEMS, and electronic related applications. Standard techniques for polishing of diamond are extremely slow because of its extreme hardness and chemical inertness. Several non conventional techniques such as laser irradiation and ion beam polishing have been developed, however none of the methods achieve sub 100 nm surface roughness over large areas. Conventional mechanical polishing techniques have also been developed, however these techniques are also not able to achieve sub nanometer surface roughness. We have developed a novel chemical mechanical technique to polish diamond films that is able to achieve sub nanometer surface roughness over large areas. This technique is based on mechano-chemical reaction of the diamond surface using unique chemistries and particles. This technique has been applied successfully to both microcrystalline and nanocrystalline films to achieve such surfaces. The effect of various polishing parameters including pressure, pH and, slurry chemistry has been investigated in detail. The final surface roughness was found to depend on the microstructure of the film. This talk will focus on the novel methodology applied and the surface quality as a function of the polishing parameters.
6:00 PM - E3.8
Quantification of Pump Induced Stresses on CMP Slurries by Rheological Measurements.
Aniruddh Khanna 1 , Purushottam Kumar 2 , Jaeseok Lee 1 , Myoung Hwan Oh 1 , Rajiv Singh 1
1 Materials Science & Engineering, University of Florida, Gainesville, Florida, United States, 2 , Sinmat Inc., Gainesville, Florida, United States
Show AbstractAgglomeration of particles in slurry is a major cause of defectivity during Chemical Mechanical Planarization (CMP) process. It is well known that the stress induced by pumps during slurry circulation leads to particle agglomeration. Previous work on pump-induced agglomeration has been mostly qualitative or at best semi-quantitative. In this work, we have used rheometer, an instrument which is conventionally used to measure fluid viscosity as a function of shear stress, to quantify stresses induced by pumps during CMP slurry circulation. Different amount of shear was applied on silica slurry that was followed by cumulative oversize particle distribution measurement using an accusizer. Quantification of the stress induced by different pumps namely, positive displacement and magnetically levitated centrifugal pumps, was performed by comparison of oversize particle distribution obtained after slurry circulation with that obtained from rheometer at different shears. The shear stress in magnetically levitated centrifugal pump was calculated to be 100 times lower than positive displacement pump. Our work, for the first time, quantifies the shear stress applied by these pumps.
6:00 PM - E3.9
Non-selective, High Removal Rates STI Slurries Based on Lewis Acids Abrasives/Cationic Copolymers.
Daniela White 1 , John Parker 1 , R. Nagarajan 1
1 , Cabot Microelectronics, Aurora, Illinois, United States
Show AbstractIn this presentation we will discuss polishing performance and related mechanistic aspects of several low solids, low or high pH slurries based on Lewis acids abrasives (TiO2, ZrO2, CeO2), activated by cationic random or block-copolymers. In a typical example, a formulation containing 0.5% ZrO2 interacting with 75 ppm cationic block-copolymer, at pH = 4, resulted in a SiO2 removal rate increase of 34% and a nitride removal rate increase of 97%, as compared with the control lacking the cationic copolymer. We will provide a complex variety of analytical evidence and particle and wafers surface measurements (XPS, SEM, FT-IR, GPC, MS-TOF, surface energy) in order to support our mechanistic hypotheses. We will show with this unique system that 1:1 selectivities of oxide and nitride can be achieved with high removal rates.
Symposium Organizers
Christopher L. Borst SUNY-Albany College of Nanoscale Science and Engineering
Johann W. Bartha Technische Universitaet Dresden
Darren DeNardis Intel Corporation
Satyavolu S. Papa Rao IBM T.J. Watson Research Center
E4: CMP Consumables II
Session Chairs
Wednesday AM, April 07, 2010
Room 2000 (Moscone West)
9:30 AM - **E4.1
Acidic Slurry Approach to STI/ILD/PMD/HKMG CMP Applications.
Hugh Li 1 , Zhendong Liu 1 , Yi Guo 1 , Arun Reddy 1 , A. Scott Lawing 1 , Lee Cook 1
1 , Dow Electronic Materials, Newark, Delaware, United States
Show AbstractStill under internal review
10:00 AM - E4.2
Influence of Ionic Strength and pH-value on the Silicon Dioxide Polishing Behaviour of Slurries Based on Pure Silica Suspensions.
Kathrin Estel 1 , Ulrich Kuenzelmann 1 , Johann Wolfgang Bartha 1 , Erwin-Peter Mayer 2 , Herbert Bathel 2
1 Institute of Semiconductor, Dresden University of Technology, Dresden, Saxony, Germany, 2 , Wacker Chemie AG, Burghausen, Bavaria, Germany
Show AbstractIn this study, the effect of the addition of electrolytes in a given ionic strength to various high-purity silica suspensions was investigated by measurement of the removal rates (RR’s) in CMP processes on oxide layers under the same experimental conditions. As so-called slurries the following suspensions were used: i) silica sols produced by the Stöber process, ii) conventional silica sols based on alkali silicate as well as iii) suspensions of fumed silica, with the same SiO2 concentration in each suspension. Ionic strength of the added electrolyte was adjusted to e.g. 0.065 mol/l, with the electrolytes being HCl, NH4Cl, KOH, or binary mixtures of these substances. These investigations revealed significant differences of the polishing behaviour caused by the different types of silica dispersions as slurries. While for the Stöber sols investigated, the RR’s are highest in the acidic range and almost negligible in the alkaline pH range, fumed silica suspensions show an entirely different behaviour: RR is very low for acidic pH-values, and increases with the alkalinity of the slurry. In contrast to these observations, the RR’s of slurries based on conventional silica sols are highest around the neutral point, and show a decrease for both more alkaline and acidic pH-values. In comparison to the other two types of material, these suspensions have a high amount of electrolyte background, originating from their manufacturing process.A model is developed to explain these results in a comprehensive manner. It involves effects of the electrolyte type and the ionic strengths as well as influences of the particle size and concentration.
10:15 AM - E4.3
Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP).
Duane Boning 1 , Joy Johnson 1 , Gwang-Soo Kim 2 , Karson Knutson 2
1 EECS, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractIn this work we propose a particle agglomeration model for chemical mechanical planarization (CMP) under the primary motivation of understanding the creation and behavior of the agglomerated slurry abrasive particles during the CMP process, which are a major cause of defectivity and poor consumable utility due to sedimentation. The proposed model considers the slurry composition as a colloidal suspension of charged colloidal silica in an electrically neutral aqueous electrolyte. First, a theoretical relationship between the measurable chemical parameters of the slurry’s aqueous electrolyte, the surface potential of the abrasive particles, and corresponding zeta potential between the agglomerated abrasive particles is presented. Secondly, this zeta potential is used in a modified DVLO interaction potential model to determine the particle interaction potentials due to both the attractive van Der Waals forces and repulsive electrostatic interactions. Finally, the total interaction potential created is then used to define a stability ratio for slow versus fast agglomeration and corresponding agglomeration rate equations between particles; these are used in a discrete population balance framework to describe the final particle size distribution with respect to time and agglomerate composition. The proposed model will provide both a qualitative and quantitative description of agglomeration of abrasive slurry particles during CMP that can be extended to account for slurry composition or abrasive particle type, enabling more accurate process control, increased consumable utility, and possible defectivity reduction.
10:30 AM - E4.4
Mechanistic Investigations of Ruthenium Polishing Enabled by Heterogeneous Catalysis With Titania-based Slurries.
Daniela White 1 , John Parker 1 , R. Nagarajan 1
1 , Cabot Microelectronics, Aurora, Illinois, United States
Show AbstractDifficulties and challenges have been widely encountered in the chemical mechanical planarization (CMP) of noble metals used as diffusion barrier films due to hardness, chemical inertness and toxic oxidation products, in particular for Ru polishing. A commercial CMC Ru polishing slurry that successfully addressed the safety concerns was based on a high pH (8.4) polymer-treated α-alumina-based multi-additive slurry containing complexing reagents (carboxylic acids and salts), corrosion inhibitors, surfactants, and hydrogen peroxide as a mild, non-aggressive oxidizer. Recently, our efforts had been redirected towards the development of a new generation of low pH barrier slurries based on an entirely new concept employing unique Lewis acid type abrasives. This class of materials is well known to be highly reactive in dielectrics polishing (ceria, zirconia, titania), but far less is known about their interactions with Ru, Cu or Ta.In this presentation, we will elaborate the unexpected discovery that hard, chemically inert, noble metals such as ruthenium can be polished easily by virtually abrasive-free and/or oxidizer-free TiO2 based slurries. Of particular importance is the finding that the polymorphic phase of TiO2 (anatase or rutile), its surface chemistry (functional groups, Lewis acid/base character), pH induced surface modification and reactivity, can all mediate the abrasive particle’s adsorption properties, catalytic activity and ultimately, its slurry polishing performance.We will also demonstrate that rutile TiO2 was the polymorphic phase of choice due to the high concentration of surface hydroxyl groups and fully oxidized T4+ cations, able to create and sustain a highly Lewis acidic surface needed for an optimum chemisorption of the oxidizer, in order to further efficiently dissociate into high energy oxidizing radicals. Both the FTIR-ATR and XPS/Auger surface analysis on the polished ruthenium wafers surface revealed the presence of mixed oxides Ti/Ru as much as 30 Å in depth. At low pH, the reaction kinetics are mostly driven by a finite number of active, catalytic centers at both: particle/water interface (Ti4+, Ti-OH, Ti-O-Ti)), and on the ruthenium wafer surface, very prone to reversible and unique three-way interactions with the oxidizer, by continuously generating a constant number of reactive radicals on the particle surface, immediately delivered in the aqueous phase towards the metal oxidation, without any substantial catalytic reactivity loss. Reversible formation of both the superoxide radical anions on the particle/catalyst surface and reduced Ti3+ cations on the wafer surface, simultaneously occurs with the Ru metal oxidation and TiO2 surface regeneration towards chemisorption of more oxidizer, generating of new surface active radicals, etc.
11:15 AM - **E4.5
Role of Different Additives in Ceria and Silica-based Slurries for Achieving Tunable Removal Rates of Silicon Oxide, Silicon Nitride and Polysilicon.
Suryadevara Babu 1 , Veera P.R. Dandu 1 , Naresh Penta 1
1 , Clarkson Univversity, Potsdam, New York, United States
Show AbstractIt will be shown that several amino acids and cyclic amines, when added to ceria- and silica-based slurries, have a dramatic influence on the polish rates of silicon dioxide, silicon nitride and poly-Si films. For example, any one of the cyclic amines, pyridine HCl, piperazine or imidazole, even when present only at low concentrations (0.05wt %) in a ceria-based slurry, yields a high oxide (~ 350nm/min) and low nitride (~ 2nm/min) removal rate. Similarly, by adding arginine or lysine mono hydrochloride to either colloidal silica or ceria slurries, one can obtain poly-Si removal rate of ~550nm/min while the oxide and nitride removal rates are both lowered to a few nm/min. Several polymer additives - poly(ethyleneimine), poly(diallyldimethyl ammonimumchloride), poly(acrylicacid-co-diallyldimethyl ammonimumchloride), poly(acrylamide-co-diallyldimethyl ammonimumchloride), etc. - at < 250ppm can also be used to obtain similar results, for example, either to suppress the oxide, but not the nitride, removal rate, or to suppress one or both while maintaining a high poly-Si removal rate, leading to a reverse selectivity or highly tunable poly-Si/oxide/nitride removal rates, respectively. In all cases, the suppression of the oxide removal rate seems to be related to the suppression of the Ce3+ ion concentration. The role of these additives on oxide and nitride RRs were investigated using data on zeta potentials, contact angles and adsorption isotherms, and TGA, FTIR, and UV-Visible spectroscopy.
11:45 AM - E4.6
Increase in the Adsorption Density of Anionic Molecules on Ceria and Its Influence on Remaining Particles on Oxide Film During Shallow Trench Isolation (STI) Chemical Mechanical Planarization (CMP).
Ye-Hwan Kim 1 , Hyeonggyu Han 1 , Jeong Hyun Kim 1 , Jea-Gun Park 2 , Ungyu Paik 1
1 Department of Materials Science Engineering, Hanyang University, Seoul Korea (the Republic of), 2 Division of Nanoscale Semiconductor Engineering, Hanyang University, Seoul Korea (the Republic of)
Show AbstractThe ceria slurry offers improved selectivity for the planarization of trench fill material while leaving a polish stop layer of uniform thickness. However, it inevitably induces defects on the wafer surface, including those triggered by microscratches caused by poor dispersion of ceria particles and insufficient repulsive forces between the abrasives and film surface. These defects are a crucial issue in the STI CMP process. In this presentation, a new methodology is proposed to prevent scratches on wafer surfaces. Hydrogen citrate was used to be adsorbed onto the vacant adsorption sites between the carboxylate groups in the PMMA, which led to an increase in the adsorption density of anionic molecules on the ceria surface. The influence of hydrogen citrate on the surface potential of the ceria particles was observed in the presence of PMMA by increasing the hydrogen citrate concentration. A correlation between the increase in the adsorption density of anionic molecules on ceria particles and CMP performance was seen, which verified that our methodology was effective for preventing the formation of microscratches during the STI CMP process.
12:00 PM - E4.7
The Mechanism of Low pH Colloidal Silica-based Oxide Slurries.
Michael White 1 , William Ward 1 , R. Nagarajan 1 , Laman Jones 1
1 , Cabot Microelectronics, Aurora, Illinois, United States
Show AbstractThe use of high pH oxide slurries such as Semi-Sperse® SS25 to polish various forms of silicon dioxide wafers at high rates has been prevalent for many years. However, typically such an approach uses fumed silica at silica concentrations exceeding 10%. Much lower removal rates are obtained with colloidal silica at similar concentrations. For instance, fumed silica yields a removal rate of 2700 Å/min on TEOS while colloidal silica has a removal rate of 410 Å/min at pH 12. At pH 4, the removal rate for colloidal silica is a mere 90 Å/min. However, the addition of cationic rate additives can increase the TEOS removal rate to 3000 Å/min at the same CMP process and at less than half the solids of fumed silica based slurries while maintaining low defectivity (DCN/DCO < 50 at 225 nm). This represents a removal rate of over 30 times that of colloidal silica without the rate additives. The mechanism of the rate acceleration is believed to involve the inversion of the negative charge on the particle surface yielding a coulombic attraction between the particle and the wafer thus lowering the activation energy and dramatically increasing the removal rate. This mechanism is supported by zeta potential titrations on the particle and streaming potential measurements on the charge on the wafer surface. In addition, this slurry can be tuned to give a 1:1 selectivity between silicon and silicon dioxide removal rates. The mechanistic implications of this phenomenon will be discussed.
12:15 PM - **E4.8
Mechanisms of Large Particle Formation in Silica-based CMP Slurries Resulting in Mechanical and Chemo-mechanical Induced Defects.
W. Rader 1 , Tim Holt 1 , Kazusei Tamai 2
1 , Fujimi Corp, Tualatin, Oregon, United States, 2 , Fujimi Inc, Nagoya Japan
Show AbstractWhile the generation of mechanical and chemo-mechanical defects are believed to result from large particles, the mechanisms of large particle formation and its relationship to specific types of defects is not clear. Polishing tests, microscopy and an improved large particle metrology were utilized to identify, predict and reduce the occurrence of mechanical and chemo-mechanical defects. Particle characteristics, slurry chemistry and processing conditions were investigated to understand their contribution to large particle formation.
E5: Novel CMP Techniques & Devices
Session Chairs
Wednesday PM, April 07, 2010
Room 2000 (Moscone West)
2:30 PM - **E5.1
Using Combinatorial Methods to Accelerate BEOL Wafer Cleaning Process Development.
Trace Hurd 1 , Jeff Barnes 1 , Jun Liu 1 , Steve Medd 1 , Steve Lippy 1 , Steve Bilodeau 1 , Peter Wrschka 1 , Yukichi Koji 1 , Rekha Rajaram 2 , Don Canaperi 3
1 , ATMI, Danbury, Connecticut, United States, 2 , Intermolecular, San Jose, California, United States, 3 , IBM, Albany, New York, United States
Show AbstractAs devices geometries shrink with each pass technology node, the challenges for BEOL wafer cleaning continue to grow. In addition to simple design shrinkage which drives a continuing need for ever decreasing defect levels, the ongoing introduction of new materials further complicates the situation via the addition of additional cleaning process requirements. Cleans must now remove CMP slurries or etch residues selectively to ULK dielectrics, new barriers, and hardmask metals while still being compatible with standard dielectrics, Cu, TaN, and W. Such cleans must also show no increase in k value for dielectrics in the 2.2 - 2.7 class, maintain a stable Cu surface, and result in no increase in line to line leakage following the clean. Finally, as BEOL integration schemes diverge at manufacturers (e.g. hard mask and Cu capping) additional challenges arise with respect to the selectivity requirements imposed on the cleans and final wafer surface state that is desired.Given the above challenges facing the industry as it moves into the 22nm node and beyond, it is becoming increasingly important to be able to rapidly adapt cleans chemistries and strategies to match each integration option being evaluated and deployed in a particular manufacturing line. The ability to not only generate tailored solutions that meet physical requirements but to also rapidly demonstrate scale up and electrical viability while on a tight silicon budget will be enabling in the years to come.In this paper, new approaches to driving from cleans design strategy to rapid scale up and electrical characterization will be described, including recent examples that demonstrate their feasibility and effectiveness. Special focus will be given to post CMP cleans formulations and how they can be rapidly modified to adapt to the specific needs of a particular integration scheme.Two primary examples will be described. In both cases, modification of an existing PCMP clean product was required in order to make it optimal for a given integration scheme. In the first case, improvements in metal removal from dielectric were requested and accommodated without impacting the cleaning performance of the chemistry. In the second, it was necessary to optimize a process and formulation between achieving the desired degree of surface passivation without driving an offsetting increase in organic defects.
3:00 PM - E5.2
Characterization of Surface Processes During Oxide CMP by in situ FTIR Spectroscopy With Microstructured Reflection Elements at Silicon Wafers.
Henrik Schumacher 1 , Ulrich Kuenzelmann 1 , Johann Bartha 1
1 Intitute of Semiconductor and Microsystem Technology, Dresden University of Technology, Dresden, Saxony, Germany
Show AbstractThe fundamental investigation of chemical and mechanical mechanisms in CMP requires the access to the wafer surface interacting with the slurry under polishing conditions. A possible analytical technique, which utilises the IR transparency of silicon is Fourier transform infrared (FTIR) spectroscopy. It provides structural information about molecular vibrations of characteristic groups. In this study we make use of a novel, specifically prepared Si wafer enabling in and ex situ FTIR investigations by attenuated total reflection (ATR) at the interface between silicon and the ambient, which in our case was a thin oxide layer and the polishing slurry. During that internal reflection an evanescent wave penetrates the ambient. The reflected beam contains information about the oxide layer and the polishing slurry within a depth ranging around one micron in the mid IR.Arrays of v-shaped groves prepared by crystal oriented anisotropic wet etching at the backside of common silicon wafers are used as coupling structures for the IR radiation. These wafers, called microstructured single reflection elements (mSRE), were placed at a simple reflection accessory of a FTIR spectrometer and polished using a CMP equivalent polishing configuration. During the CMP of SiO2 layers on mSRE’s with silica and ceria slurries intensity and shape of the oxide vibration bands provide information about changes of oxide thickness, composition and structure. Furthermore, slurry constituents with characteristic bands influenced by particle sizes, shape and aggregation could be detected. A significant finding is that spectral features of the pad have not been observed during the polishing investigations.It was shown that the high sensitivity as well as the surface selectivity of the experimental setup enables surface characterisations within the thickness range of monolayers. With such kind of in situ investigations dynamic effects i.e. slow start and agglomeration are better accessible. The experimental results contribute to theoretical models of chemical and mechanical interactions between oxide layers and constituents of the slurry. Our mSRE’s as used in these investigations are applicable for a broad variety of applications in IC manufacturing.
3:15 PM - E5.3
An Alternative Non-contact Planarization Technique by Utilizing the Electrokinetic Phenomenon.
Cheng Seng Leo 1 , Sum Huan Ng 2 , David Butler 1 2 , Steven Danyluk 3
1 Mechanical & Aerospace Engineering, Nanyang Technological University, Singapore Singapore, 2 , Singapore Institute of Manufacturing Technology, Singapore Singapore, 3 George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractChemical Mechanical Planarization (CMP) has been the dominant means of achieving planarization on a wafer and is well-known to have a strong influence on other downstream processes. However, CMP usually suffers a wide range of issues such as micro-scratching, dishing and erosion on the wafers which can be attributed to fact that it is a contact material removal process. With the increasing demand of producing thinner wafers with even finer features, improvements to the present CMP process have to be made to tackle these inevitable issues. In this paper, the authors will introduce an alternative non-contact material removal technique which overcomes some of the limitations of the CMP process. Material removal is made possible by utilizing the electrokinetic and hydrodynamic effects of suspended particles to manipulate their trajectories to impact onto the surface of the workpiece. The research was previously demonstrated and reported where the removal rate can be precisely controlled by varying the electrical field and the flow rate of the slurry across the surface of the workpiece. New findings will be reported on the application of the technique to different materials which will highlight the attractiveness of this alternative approach to producing surfaces with roughness in the order of nanometres. Furthermore, the technique is currently being refined to achieve material removal over a larger area with the intention of providing a possible substitute for the incumbent CMP process.
3:30 PM - **E5.4
Characterization and Modeling of Pad Asperity Response in CMP.
Duane Boning 1 , Wei Fan 1
1 Microsystems Technology Laboratories, MIT, Cambridge, Massachusetts, United States
Show AbstractModeling of the chemical-mechanical polishing (CMP) of patterned wafers typically uses implicit or explicit assumptions about the polishing pad and its mechanical properties. Parameters that are believed to be important for understanding feature and die planarization results include the bulk pad Young's modulus and the asperity height distribution, among others. In this work, we consider the pad surface structure in more detail. Using nanoindentation studies, we probe the mechanical response of pad surface asperities, to better understand asperity interactions with the surface of the wafer during polishing. The force-deflection response is particularly relevant to patterned wafer models of dishing and erosion that are based on removal rate as a function of feature height, pattern density, and effective local pressures.
4:30 PM - E5.5
Contact Pressure Distribution in the Chemical Mechanical Planarization of 450mm Wafers.
Padraig Timoney 1 , Eamonn Ahearne 1 , Gerald Byrne 1
1 Advanced Manufacturing Science Research Centre, School of Electronic, Electrical and Mechanical Engineering, University College Dublin, Dublin Ireland
Show AbstractOptimisation of spatial uniformity of material removal in chemical mechanical planarization requires an understanding of the mechanics of the wafer carrier system. Finite element analysis results, validated by experiments, have been reported by researchers identifying relationships between von Mises stress distribution and material removal rate; implying also its spatial uniformity and the effects of the edge discontinuity. However, in many of these wafer scale models, the derivation of the material properties of the polishing pad and sub pad is unclear and consequently a large variation in values used is observed. Models are generally validated with a procedure different to that simulated in the model and with different output variables. Few models have incorporated the industry standard method of pressurizing the backside of the wafer independently to the wafer carrier loading using a pressurized air chamber located directly behind the backside of the wafer. The anticipated introduction of 450mm diameter wafers has surprisingly not been accompanied by wafer scale models investigating the issues that will arise from the diameter and thickness scaling ratio of the wafer. This paper presents a unique approach to finite element modeling of CMP incorporating realistic boundary conditions for the wafer carrier and platen assemblies. Model predictions of interfacial contact pressure for a 200mm wafer loaded by a lip seal type carrier head were validated by unique measurements of the contact pressure between the wafer and the pad using Fujifilm Prescale TM pressure measurement film and accompanying analysis software. The results demonstrated a close correlation between the model’s prediction and the measured values. Results are presented for the upscaling of this validated model to 450mm wafer dimensions. The results indicate a doubling of the contact pressure maximum and average values compared to the 200mm wafer model. These results illustrate the extent of the challenge facing CMP tool vendors in increasing the level of control of the mechanical force distributed by the wafer carrier on 450mm wafers. The model can be used as a design tool to optimize machine and process parameters e.g. polishing pad thickness.
4:45 PM - E5.6
Microlens Topography Fabricated Using CMP for Enhanced Light Extraction From LEDs.
Purushottam Kumar 1 , Rajiv Singh 2 , Deepika Singh 1
1 , Sinmat Inc., Gainesville, Florida, United States, 2 Materials Science & Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractOne of the challenges in the field of solid state lighting is the enhancement of brightness to >200 lumens/watt. External efficiency of light emitting devices is limited primarily by the out-coupling efficiency of the device. High refractive index and the planar nature of the substrates lead to total internal reflection and wave-guiding of a majority of generated photons, thus severely limiting the external efficiency of these devices. Currently, diffuse scattering from rough surfaces created by various etching techniques is used to reduce wave-guiding. We have used Chemical mechanical planarization, a standard technique for surface preparation to create non-planar surface topographies. The non-planar surface significantly reduces the wave-guiding of photons, hence enhancing the efficiency. In this study we have used the phenomena of dishing and edge rounding, conventionally considered CMP defects, for fabrication of different topographies on SiC and GaN substrates and films. The effect of CMP variables; pad and pressure on the surface topography were studied. The surface evolution dynamics for creation of different curvature and aspect ratio structures during polishing will be discussed based on contact mechanical model for CMP. Monte Carlo ray tracing simulations predicts a light out-coupling enhancement of over three times compared to planar substrates with the use of microlens topography. Correlation between simulated data and experimental results from non-planar surfaces will be discussed in detail.
5:00 PM - **E5.7
How Much Slurry is Sufficient?
Len Borucki 1 , Yasa Sampurno 1 , Sian Theng 1 , Ara Philipossian 1 2
1 , Araca Inc, Tucson, Arizona, United States, 2 Department of Chemical and Environmental Engineering, The University of Arizona, Tucson, Arizona, United States
Show AbstractThe two most expensive CMP consumables are slurry and pads. These together can account for 70% of the cost of processing with slurry often being the larger share. Yet theoretical analyses of actual slurry requirements and effective methods for reducing consumption have lagged behind other process improvements.We show here that for any given rotary tool design and slurry application method, the slurry flow rate needed on a larger tool can be estimated from the empirically determined flow rate on a smaller tool. The estimate, based on the thin film equation, produces a scaling law that says that if the contact pressure and sliding speed are held constant during a process transfer, then the slurry flow rate should scale like the ratio of the pad areas times the inverse ratio of the mean distance between the wafer center and the pad center. This scaling law is in agreement with empirical flow rates used in 200 mm and 300 mm processing and provides a prediction of slurry requirements at 450 mm.For a given tool, it is still a problem to find a slurry application method that significantly reduces consumption without negative side effects. One reason is mixing. When slurry is applied from a single nozzle, there is evidence that the removal rate can be affected by moving the application point around. However, the maximum achievable removal rate increase depends on the interaction of the conditioner with the fresh slurry puddle, suggesting that the conditioner may affect rates by mixing used and fresh slurry.A second issue is that excess fresh slurry can form a bow wave at the leading edge of the wafer or retaining ring. The carrier then advects the excess slurry toward the edge of the pad where most of it is lost. Because of the bow wave, slurry utilization efficiency is generally very low. Reducing the slurry flow rate reduces the bow wave volume and increases utilization efficiency. The best efficiency would be obtained just above the starvation point. However, simulations suggest that starvation onset occurs at very low flow rates, making it impractical for flow rate determination because of the defectivity risk.Considering the effect of mixing and bow wave loss on removal rates and slurry utilization, we have developed a slurry application device that addresses the shortcomings of methods that rely on single or multiple nozzles. The device, a slurry injector, minimizes fresh slurry mixing and eliminates the bow wave without inducing starvation. Slurry utilization efficiency with the injector can be in excess of 90%. At all flow rates we measure a higher removal rate with the injector than with point application. Removal rate vs. flow rate data indicate that slurry flow rates using the injector can be reduced by 40-50% for TEOS and 60% or more for copper polishing with no sacrifice in removal rate. Defectivity and non-uniformity are at least as good and often better than with normal application methods.